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IMPORTANT NOTICE
Dear customer, As from August 2nd 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document.
Company name - NXP B.V. is replaced with ST-NXP Wireless. Copyright - the copyright notice at the bottom of each page "(c) NXP B.V. 200x. All rights reserved", shall now read: "(c) ST-NXP Wireless 200x - All rights reserved". Web site - http://www.nxp.com is replaced with http://www.stnwireless.com Contact information - the list of sales offices previously obtained by sending an email to salesaddresses@nxp.com , is now found at http://www.stnwireless.com under Contacts.
If you have any questions related to the document, please contact our nearest sales office. Thank you for your cooperation and understanding. ST-NXP Wireless
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ISP1302
Universal Serial Bus On-The-Go transceiver with carkit support
Rev. 01 -- 24 May 2007 Product data sheet
1. General description
The ISP1302 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver device that supports USB Carkit Specification (CEA-936-A), November 2005. It is fully compliant with Universal Serial Bus Specification Rev. 2.0 and On-The-Go Supplement to the USB Specification Rev. 1.2. The ISP1302 can transmit and receive serial data at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) data rates. The ISP1302 is available in HVQFN24 and WLCSP25 packages.
2. Features
I Fully complies with: N Universal Serial Bus Specification Rev. 2.0 N On-The-Go Supplement to the USB Specification Rev. 1.2 N On-The-Go Transceiver Specification (CEA-2011) N USB Carkit Specification (CEA-936-A), November 2005 I Can transmit and receive serial data at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) data rates I Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) I Supports I2C-bus (up to 400 kHz) serial interface to access control and status registers I Supports Universal Asynchronous Receiver-Transmitter (UART) pass-through on the DP and DM lines I Supports service mode with 2.8 V UART signaling on the DP and DM lines I Built-in analog switches to support analog audio signals multiplexed on the DP and DM lines I Built-in DC biasing for audio signals on the DP and DM lines I Supports both 4-wire and 5-wire signaling protocol for carkit application I Supports data-during-audio mode for smart carkit application I Built-in charge pump regulator outputs 5 V at current up to 50 mA I 3.0 V to 4.5 V power supply input range (VCC) I Supports wide range digital interfacing I/O voltage (VCC(I/O)) 1.4 V to 3.6 V I Full industrial grade operation from -40 C to +85 C I Available in small HVQFN24 and WLCSP25 halogen-free and lead-free packages
NXP Semiconductors
ISP1302
USB OTG transceiver with carkit support
3. Applications
I Mobile phones I Digital camera I Personal digital assistant
4. Ordering information
Table 1. Ordering information Package Name ISP1302HN ISP1302UK Description Version SOT616-3 ISP1302UK HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm WLCSP25 wafer level chip-size package; 25 bumps; 2.5 x 2.5 x 0.6 mm Type number
ISP1302_1
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ISP1302
USB OTG transceiver with carkit support
5. Block diagram
VCC(I/O) ADR/PSW VREG VCC C_A C_B
24
1 CLOCK AND TIMER
7 3.3 V DC-DC REGULATOR
20
21
22 23 CPGND
VBUS CHARGE PUMP
SDA SCL
2 3 SERIAL CONTROLLER
VBUS COMPARATOR
19
VBUS
RESET_N
4
ID DETECTOR
18
ID
INT_N
5 CARKIT DP INTERRUPT DETECTOR LEVEL SHIFTER 6
SERVICE_N
8
CR_INT
OE_N/INT_N
9
RCV
12
AUDIO DATA CONTROL
ISP1302HN
DIF TX SE0/VM 13
16 DP 15 DM
DAT/VP
14 DIF RX
PULL-UP AND PULL-DOWN RESISTORS
SE DETECTOR
SE D+ 10 AUDIO BYPASS SE D- 11 SPKR_L SPKR_R/MIC
DGND
die pad 17
004aaa541
AGND
The figure shows the HVQFN pinout. For the WLCSP ballout, see Table 2.
Fig 1. Block diagram
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ISP1302
USB OTG transceiver with carkit support
6. Pinning information
6.1 Pinning
24 VCC(I/O) 23 CPGND
terminal 1 index area ADR/PSW SDA SCL RESET_N INT_N CR_INT 1 2 3 4 5 6
19 VBUS 18 ID 17 AGND 16 DP 15 DM 14 DAT/VP 13 SE0/VM RCV 12 12 RCV 13 SE0/VM 14 DAT/VP 15 DM 16 DP 17 AGND 18 ID VBUS 19
004aaa727 004aaa726
22 C_B OE_N/INT_N 9
21 C_A SPKR_L 10 C_A 21 10 SPKR_L
ISP1302HN
Transparent top view
Fig 2. Pin configuration HVQFN24 (top view)
CR_INT INT_N RESET_N SCL SDA ADR/PSW
6 5 4 3 2 1 VCC(I/O) 24 CPGND 23 C_B 22 VCC 20 terminal 1 DGND (exposed die pad)
ISP1302HN
terminal 1 index area
Bottom view
Fig 3. Pin configuration HVQFN24 (bottom view)
ISP1302_1
11 SPKR_R/MIC
7
8
9
OE_N/INT_N
SERVICE_N
VREG
SPKR_R/MIC 11
7
VREG
SERVICE_N
8
20 VCC
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ISP1302
USB OTG transceiver with carkit support
ball A1 index area A B C D E
ISP1302UK
1 2 3 4 5
004aaa716
Fig 4. Pin configuration WLCSP25 (top view)
ISP1302UK
ball A1 index area
004aaa706
Fig 5. Pin configuration WLCSP25 (bottom view)
6.2 Pin description
Table 2. Symbol[1] ADR/PSW Pin description Pin Ball Type[2] HVQFN24 WLCSP25 1 C1 I/O Reset value high-Z Description ADR input -- Sets the least-significant I2C-bus address bit of the ISP1302; latched on the rising edge of the RESET_N pin PSW output -- Enables or disables the external charge pump after reset An internal series resistor is implemented for this pin. If the PSW (output) function is not used, then this pin can directly be connected to DGND or VREG. This pin will output 3.3 V when driven HIGH. For details, see Section 7.13. bidirectional; push-pull input; 3-state output SDA SCL RESET_N INT_N 2 3 4 5 D2 D3 C2 B1 I/OD I/OD I OD high-Z high-Z high-Z serial I2C-bus data input and output bidirectional; push-pull input; open-drain output serial I2C-bus clock input and output bidirectional; push-pull input; open-drain output asynchronous reset input, active LOW interrupt output; active LOW open-drain output
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ISP1302
USB OTG transceiver with carkit support
Table 2. Symbol[1] CR_INT VREG
Pin description ...continued Pin Ball Type[2] HVQFN24 WLCSP25 6 7 8 C4 A2 A1 AI P I Reset value Description directly connect to the DP pin of the USB connector; if the carkit feature is not used, this pin can be connected to ground output of the voltage regulator; place a 0.1 F capacitor between this pin and ground input; sets default operation mode of the ISP1302:
SERVICE_N
* *
If a LOW is latched on reset (including power-on reset), default mode is UART with 2.8 V signaling. If a HIGH is latched on reset (including power-on reset), default mode is USB with 3.3 V signaling.
Operation mode can be changed after reset by changing the value of the Mode register bits. OE_N/INT_N 9 B3 I/O high-Z this pin can be programmed as: OE_N input -- Enables driving DP and DM when in USB mode INT_N output -- Indicates interrupt when bit OE_INT_EN = 1 and SUSPEND_REG = 1 bidirectional; push-pull input; 3-state output SPKR_L SPKR_R/MIC 10 11 A3 A4 AI AI/O analog audio input signal for the left speaker channel; connect to ground if not in use analog audio input signal for the right speaker channel or audio output signal for the microphone channel; connect to ground if not in use differential receiver output; reflects the differential value of DP and DM push-pull output SE0/VM 13 B4 I/O high-Z SE0 input and output -- SE0 functions in DAT_SE0 USB mode VM input and output -- VM functions in VP_VM USB mode TxD input -- UART mode bidirectional; push-pull input; 3-state output DAT/VP 14 B5 I/O high-Z DAT input and output -- DAT functions in DAT_SE0 USB mode VP input and output -- VP functions in VP_VM USB mode RxD output -- UART mode bidirectional; push-pull input; 3-state output DM 15 D5 AI/O high-Z this pin can be programmed as:
RCV
12
A5
O
0
* * *
DP 16 D4 AI/O high-Z
USB D- (data minus pin) transparent UART TxD or transparent audio SPKR_L USB D+ (data plus pin) transparent UART RxD or transparent audio SPKR_R/MIC
this pin can be programmed as:
* * *
AGND 17 C3 P -
analog ground
ISP1302_1
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Product data sheet
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ISP1302
USB OTG transceiver with carkit support
Table 2. Symbol[1] ID VBUS
Pin description ...continued Pin Ball Type[2] HVQFN24 WLCSP25 18 19 C5 E5 AI/O AI/O Reset value high-Z Description identification detector input and output; connected to the ID pin of the USB mini receptacle; internal 100 k pull-up resistor VBUS line input and output of the USB interface; charge pump output; place an external decoupling capacitor of 0.1 F close to this pin supply voltage (3.0 V to 4.5 V) charge pump flying capacitor pin 2; connect a 220 nF capacitor between C_B and C_A for 50 mA output current charge pump flying capacitor pin 1; connect a 220 nF capacitor between C_B and C_A for 50 mA output current ground for the charge pump supply voltage for the I/O interface logic signals (1.4 V to 3.6 V) digital ground
VCC C_A C_B CPGND VCC(I/O) DGND
20 21 22 23 24 exposed die pad
E4 E3 E2 E1 D1 B2
P AI/O AI/O P P P
-
[1] [2]
Symbol names ending with underscore N (for example, NAME_N) indicate active LOW signals. AI = analog input; AI/O = analog input/output; I = input; O = output; I/O = digital input/output; I/OD = input/open-drain output; OD = open-drain output; P = power or ground.
ISP1302_1
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ISP1302
USB OTG transceiver with carkit support
7. Functional description
7.1 Serial controller
The serial controller includes the following functions:
* * * * *
Serial controller interface Device identification registers Control registers Interrupt registers Interrupt generator
The serial controller acts as an I2C-bus slave, and uses the SCL and SDA pins to communicate with the OTG Controller. For details on the serial controller, see Section 9.
7.2 VBUS charge pump
The charge pump supplies current to the VBUS line. It can operate in any of the following modes:
* Output 5 V at current above 50 mA * Pull-up VBUS to 3.3 V through a resistor (RUP(VBUS)) to initiate VBUS pulsing SRP * Pull-down VBUS to ground through a resistor (RDN(VBUS)) to discharge VBUS 7.3 VBUS comparators
VBUS comparators provide indications regarding the voltage level on VBUS.
7.3.1 VBUS valid comparator
This comparator is used by an A-device to determine whether the voltage on VBUS is at a valid level for operation. The minimum threshold for the VBUS valid comparator is 4.4 V. Any voltage on VBUS below this threshold is considered a fault. A hardware debounce timer (td(VA_VBUS_VLD)) is implemented for the VBUS valid comparator. This timer is enabled when the internal charge pump is turned on (bit VBUS_DRV = 1) and is disabled when the internal charge pump is turned off (bit VBUS_DRV = 0). During power-up, it is expected that the comparator output will be ignored.
7.3.2 Session valid comparator
The session valid comparator is used to determines when VBUS is high enough for a session to start. Both the A-device and the B-device use this comparator to detect when a session is started. These devices also use this comparator to indicate when a session is completed. The session valid threshold is between 0.8 V to 2.0 V for A-device, and between 0.8 V to 4.0 V for B-device.
7.3.3 Session end comparator
The session end comparator determines when VBUS is below the B-device session end threshold of 0.2 V to 0.8 V.
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ISP1302
USB OTG transceiver with carkit support
7.4 ID detector
In normal power mode (when both VCC and VCC(I/O) are present), the ID detector senses the condition of the ID line and can differentiate between the following conditions:
* The ID pin is floating (bit ID_FLOAT = 1). * The ID pin is shorted to ground (bit ID_GND = 1). * The ID pin is connected to ground through resistor RDN(ID) = 102 k (bit
ID_102K = 1).
* The ID pin is connected to ground through resistor RDN(ID) = 200 k (bit
ID_200K = 1).
* The ID pin is connected to ground through resistor RDN(ID) = 440 k (bit
ID_440K = 1). In power-down mode, only ID_FLOAT detector is active and can wake-up the chip. The remaining detectors are turned off. Table 3 shows the type of device connected, depending on the status of the ID and VBUS pins.
Table 3. 0 0 0 1 1 1 ID pin status for various applications ID_FLOAT 1 0 0 0 0 1 ID_GND 0 1 0 0 0 0 ID_102K 0 0 1 0 0 0 ID_200K X 0 0 1 0 0 ID_440K X 0 0 0 1 0 Device connected nothing connected OTG A-device phone accessory charger type 1 charger type 2 carkit or PC
SESS_VLD
The recommended procedure to detect the ID status using software is: 1. When nothing is connected, ID is floating and ID_FLOAT = 1. The chip can be set in power-down mode. 2. Enable the ID_FLOAT (rising edge and falling edge) and SESS_VLD (rising edge) interrupts. 3. If a plug that causes a change in ID_FLOAT or SESS_VLD is inserted, an interrupt occurs. Interrupt Latch register bit ID_FLOAT or SESS_VLD is set. 4. The software waits for sometime, for example: 100 ms, to allow mechanical debounce. 5. The software reads the Interrupt Source register and the OTG Status register, and checks bits SESS_VLD, ID_GND, ID_102K, ID_200K and ID_440K. 6. The device type is determined according to Table 3. The ID detector has a switch that can be used to ground pin ID. This switch is controlled by bit ID_PULLDN of the OTG Control register, and bits PH_ID_INT and PH_ID_ACK of the Audio Control register. See Table 4.
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ISP1302
USB OTG transceiver with carkit support
ID pull-down control 0 0 1 1 X 0 1 0 1 X off on for time tPH_ID_INT, then off and bit PH_ID_INT autoclears to 0 wait for time tPH_ID_WT, turn on the switch for tPH_ID_INT, then off and bit PH_ID_ACK autoclears to 0 not defined on
Table 4. 0 0 0 0 1
ID_PULLDN PH_ID_ACK PH_ID_INT Switch between ID and ground
7.5 Pull-up and pull-down resistors
Figure 6 shows the switchable pull-up and pull-down resistors that are internally connected to the DP and DM lines. The DP pull-up resistor (SW1) is controlled by bit DP_PULLUP of the OTG Control register. The pull-up resistor is context variable as described in document ECN_27%_Resistor. The pull-up resistor value depends on the USB bus condition:
* When the bus is idle, the resistor is 900 to 1575 (SW2 = on). * When the bus is transmitting or receiving, the resistor is 1425 to 3090
(SW2 = off). DP also implements a weak pull-up resistor (RweakUP(DP)) that is controlled using bit DP_WKPU_EN of the Misc Control register. The DP pull-down resistor (RDN(DP)) is connected to the DP line, if bit DP_PULLDOWN in the OTG Control register is set. The DM pull-down resistor (RDN(DM)) is connected to the DM line, if bit DM_PULLDOWN in the OTG Control register is set.
ISP1302_1
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ISP1302
USB OTG transceiver with carkit support
VREG
0.525 k to 1.515 k
SW2 RweakUP(DP) 150 k 30 %
0.525 k to 1.515 k
SW2
SW1
SW3
SW1
0.9 k to 1.575 k
0.9 k to 1.575 k
DP DM
DP_PULLDOWN
DM_PULLDOWN
15 k (14.3 k to 24.8 k)
RDN(DP)
RDN(DM)
15 k (14.3 k to 24.8 k)
004aaa658
AGND
AGND
Fig 6. DP and DM pull-up and pull-down resistors
7.6 3.3 V DC-DC regulator
The built-in DC-DC regulator conditions the input power supply (VCC) for use in the core of the ISP1302. When VCC is greater than 3.6 V, the regulator will output 3.3 V 10 %. When VCC is less than 3.6 V and bit REG_BYPASS_DIS = 0, the regulator will be automatically bypassed so that pin VREG will be shorted to pin VCC. When VCC is less than 3.6 V and bit REG_BYPASS_DIS = 1, the regulator will output a voltage between VCC and VCC - 0.2 V. The output of the regulator can be monitored on pin VREG. A capacitor (0.1 F) must be connected between pin VREG and ground.
7.7 Carkit DP interrupt detector
The carkit DP interrupt detector is a comparator that detects the carkit interrupt signal on the CR_INT pin in analog audio mode. Bit DP_INT will be set if the voltage level on the CR_INT pin is below the carkit interrupt threshold Vth(DP)L (0.4 V to 0.6 V). The carkit interrupt detector is enabled in audio mode only (bit AUDIO_EN = 1).
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ISP1302
USB OTG transceiver with carkit support
7.8 Audio bypass
The audio bypass block includes audio switches and DC bias circuits, see Figure 7. Audio switches provide a low impedance path for analog audio signals from the phone processor to be routed to the DP and DM lines. The impedance of the switches will be between 50 and 150 . Figure 7 shows audio switches and DC biasing circuits.
VREG
SPKR_R_ BIAS_EN
RB2
S1 SPKR_R/MIC
DP
RB1
SPKR_MIC_EN
AGND VREG SPKR_L_ BIAS_EN
RB2
SW_MIC_ SPKR_L
S3 SPKR_L
DM
RB1
SPKR_L_EN
AGND
004aaa628
Fig 7. Audio bypass
7.9 Audio data control
Figure 8 shows a diagram that includes the audio data controller. Each block within the audio data controller is described in the following subsections.
ISP1302_1
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ISP1302
USB OTG transceiver with carkit support
60 MHz CLOCK TXD TXD PULSE GENERATOR SPRK_L_EN AUDIO TIMER DM
SE0/VM
STEREO INTERRUPT DETECTOR
CARKIT INTERRUPT DETECTOR
CR_INT
DAT/VP
RXD PULSE CONVERTER
RXD
DP
004aaa629
Fig 8. Audio data control
7.9.1 Audio timer
The audio timer has two main functions. The first function is to generate the timing for the positive and negative interrupt pulses. The second function is to generate a time base that can be used to detect a carkit interrupt while in stereo mode, and reset the RxD NRZ signal during data-during-audio.
7.9.2 TxD pulse generator
The TxD pulse generator is enabled when the OTG carkit transceiver is outputting data-during-audio. When a rising or falling edge is detected on SE0/VM, the TxD pulse generator uses the AUD_TMR_OUT signal to perform the following sequence: 1. 3-state the left speaker buffer. 2. Enable the TxD buffer. 3. Output a HIGH level for the duration of the positive pulse width. 4. Output a LOW level for the duration of the negative pulse width. 5. Disable the TxD buffer. 6. Enable the left speaker buffer. The delay between a data edge on SE0/VM and a pulse pair being output on DM will jitter by as much as one audio timer period because the audio timer is free running. This is acceptable because the audio timer period is between 200 ns to 500 ns, and the UART data rate is always less than or equal to 115 kbit/s.
ISP1302_1
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ISP1302
USB OTG transceiver with carkit support
7.9.3 Stereo interrupt detector
The stereo interrupt detector generates an interrupt when the CR_INT pin has been continuously below the carkit interrupt detector threshold for a time of tPH_STLO_DET (30 ms to 100 ms); refer to USB Carkit Specification (CEA-936-A), November 2005.
7.9.4 RxD pulse converter
When data-during-audio mode is enabled, the RxD pulse converter converts the negative pulses on the DP line to an NRZ signal that is output to the DAT/VP line. Each time a pulse is received, the output on DAT/VP is inverted. If DAT/VP remains at logic 0 for a time of tDAT_AUD_POL (20 ms to 30 ms), then the output on DAT/VP will automatically return to logic 1; refer to USB Carkit Specification (CEA-936-A), November 2005.
7.10 Autoconnect
The HNP in the OTG supplement specifies the following sequence of events to transfer the role of the host from the A-device to the B-device: 1. The A-device sets the bus in the suspend state. 2. The B-device simulates a disconnect by de-asserting its DP pull-up. 3. The A-device detects SE0 on the bus and asserts its DP pull-up. 4. The B-device detects that the DP line is HIGH and assumes the role of the host. The OTG supplement specifies that the time between the B-device de-asserting its DP pull-up and the A-device asserting its pull-up must be less than 3 ms. For an A-device with a slow interrupt response time, 3 ms may not be enough to write an I2C-bus command to the ISP1302 to assert DP pull-up. An alternative method is for the A-device transceiver to automatically assert DP pull-up after detecting an SE0 from the B-device. The sequence of events is as follows: After finishing data transfers between the A-device and the B-device and before suspending the bus, the A-device sends SOFs. The B-device receives these SOFs, and does not transmit any packet back to the A-device. During this time, the A-device sets the BDIS_ACON_EN bit in the ISP1302. This enables the ISP1302 to look for SE0 whenever the A-device is not transmitting (that is, whenever the OE_N/INT_N pin of the ISP1302 is not asserted). After the BDIS_ACON_EN bit is set, the A-device stops transmitting SOFs and allows the bus to go to the idle state. If the B-device disconnects, the bus goes to SE0, and the ISP1302 logic automatically turns on the A-device pull-up. To disable the DP pull-up resistor, clear bit BDIS_ACON_EN.
7.11 USB transceiver
7.11.1 Differential driver
The operation of the driver is described in Table 5.
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ISP1302
USB OTG transceiver with carkit support
Transceiver driver operating setting Bit OE_N/INT_N SUSPEND DAT_SE0 LOW LOW 0 0 0 1 output value from DAT/VP to DP and SE0/VM to DM output value from DAT/VP to DP and DM if SE0/VM is LOW; otherwise drive both DP and DM to LOW output value from DAT/VP to DP and DM high-Z high-Z Differential driver
Table 5. Pin
RESET_N[1] HIGH HIGH
HIGH HIGH LOW
[1]
LOW HIGH X
1 X X
X X X
Include the internal power-on-reset pulse (active HIGH).
Table 6 shows the behavior of the transmit operation in detail.
Table 6. USB mode DAT_SE0 DAT_SE0 DAT_SE0 DAT_SE0 VP_VM VP_VM VP_VM VP_VM USB functional mode: transmit operation Inputs DAT/VP LOW HIGH LOW HIGH LOW HIGH LOW HIGH SE0/VM LOW LOW HIGH HIGH LOW LOW HIGH HIGH Outputs DP LOW HIGH LOW LOW LOW HIGH LOW HIGH DM HIGH LOW LOW LOW LOW LOW HIGH HIGH
7.11.2 Differential receiver
The operation of the differential receiver is described in Table 7.
Table 7. Pin OE_N/INT_N HIGH HIGH Differential receiver operation settings Bit SUSPEND 0 0 DAT_SE0 1 0 output differential value from DP and DM to DAT/VP and RCV output differential value from DP and DM to RCV Differential receiver
The detailed behavior of the receive transceiver operation is shown in Table 8.
Table 8. USB mode DAT_SE0 DAT_SE0 DAT_SE0 DAT_SE0 DAT_SE0
ISP1302_1
USB functional mode: receive operation Bit SUSPEND 0 0 0 0 1 Inputs DP LOW HIGH LOW HIGH LOW DM LOW LOW HIGH HIGH LOW Outputs DAT/VP RCV HIGH LOW RCV LOW SE0/VM HIGH LOW LOW LOW HIGH RCV last value of RCV HIGH LOW last value of RCV X
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USB OTG transceiver with carkit support
Table 8. USB mode DAT_SE0 DAT_SE0 DAT_SE0 VP_VM VP_VM VP_VM VP_VM VP_VM VP_VM VP_VM VP_VM
USB functional mode: receive operation ...continued Bit SUSPEND 1 1 1 0 0 0 0 1 1 1 1 Inputs DP HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH DM LOW HIGH HIGH LOW LOW HIGH HIGH LOW LOW HIGH HIGH Outputs DAT/VP HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH SE0/VM LOW LOW LOW LOW LOW HIGH HIGH LOW LOW HIGH HIGH RCV X X X last value of RCV HIGH LOW last value of RCV X X X X
7.12 Power-On Reset (POR)
When VCC is powered on, an internal POR is generated. The internal POR pulse width (tPORP) will typically be 200 ns. The pulse is started when VCC rises above VPOR(trip). The power-on reset function can be explained by viewing the dips at t2 to t3 and t4 to t5 on the VCC curve (see Figure 9). t0 -- The internal POR starts with a LOW level. t1 -- The detector will see the passing of the trip level and a delay element will add another tPORP before it drops to LOW. t2 to t3 -- The internal POR pulse will be generated whenever VCC drops below VPOR(trip) for more than 11 s. t4 to t5 -- The dip is too short (< 11 s) and the internal POR pulse will not react and will remain LOW.
VCC VPOR(trip)
t0
t1 tPORP
t2
t3 tPORP
t4
t5 PORP(1)
004aaa582
(1) PORP = Power-On Reset Pulse.
Fig 9. Internal power-on reset timing
7.13 I2C-bus device address and external charge pump control
The ADR/PSW pin has two functions. Both functions are described as follows.
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ISP1302
USB OTG transceiver with carkit support
The first function of the ADR/PSW pin is to set the I2C-bus address. On the rising edge of the RESET_N pin, the level on ADR/PSW is latched and stored in ADR_REG, which represents the Least Significant Bit (LSB) of the I2C-bus address. If ADR_REG = 0, the I2C-bus address for the ISP1302 is 010 1100 (2Ch); if ADR_REG = 1, the I2C-bus address for the ISP1302 is 010 1101 (2Dh). The power-on reset value of ADR_REG = 0. The second function of the ADR/PSW pin is to control an external charge pump. The ADR/PSW pin can be programmed as an active HIGH or active LOW PSW output. The polarity of the PSW output is determined by ADR_REG. If ADR_REG = 0, then PSW will be active HIGH; if ADR_REG = 1, then PSW will be active LOW. The PSW output will be enabled only when Mode Control 2 register bit PSW_OE = 1. By default, PSW can only drive HIGH if the hardware reset pulse is not issued on RESET_N. The combinations of I2C-bus address and the PSW polarity are limited, as shown in Table 9.
Table 9. Possible combinations of I2C-bus address and the PSW polarity I2C-bus address 2Ch 2Dh PSW polarity active HIGH active LOW
ADR/PSW level on the rising edge of RESET_N LOW HIGH
The ISP1302 built-in charge pump supports VBUS current at 50 mA. If the application needs more current support, an external charge pump may be needed. In this case, the ADR/PSW pin can act as a power switch for the external charge pump. Figure 10 shows an example of using an external charge pump.
VREG ADR/PSW
100 k
VBAT VIN VOUT VBUS
4.7 F
ISP1302
VBUS ON/OFF
CHARGE PUMP
USB CONNECTOR
004aaa659
Fig 10. Using an external charge pump
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USB OTG transceiver with carkit support
8. Modes of operation
The ISP1302 supports three types of modes:
* Power modes * USB modes * Transparent modes 8.1 Power modes
8.1.1 Normal mode
In this mode, both VCC and VCC(I/O) are connected and their voltage levels are within the operation range. There are three levels of power saving schemes in the ISP1302:
* Active-power mode: power is on; all circuits are active. * USB suspend mode: to reduce power consumption, the USB differential receiver is
powered down.
* Power-down mode: set by writing logic 1 to bit PWR_DN of the Mode Control 2
register. The clock generator and all biasing circuits are turned off to reduce power consumption to the minimum possible. For details on waking up the clock, see Section 10.
8.1.2 Disable mode
In disable mode, VCC(I/O) is cut-off and VCC is powered. In this mode, the ISP1302 is in the power-down state. The USB differential driver will be 3-stated as long as VCC(I/O) is not present.
8.1.3 Isolate mode
In isolate mode, VCC is cut-off and VCC(I/O) is powered. In this mode, the ISP1302 will drive a stable level to all digital output pins, and all bidirectional digital pins will be set in 3-state. Table 10 shows a summary of power modes.
Table 10. VCC Off Off On On On ISP1302 power modes summary VCC(I/O) off on off on on PWR_DN (bit) X X X 0 1 ICC = ICC(pd) yes yes yes no yes Comment power off isolate mode disable mode (power-down) normal mode (full operation) normal mode (power-down)
Table 11 shows the pin states in disable and isolate modes.
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Table 11. Pin name
ISP1302 pin states in disable and isolate modes Disable mode (VCC = on, VCC(I/O) = off) powered not present 15 k pull-down resistor enabled 15 k pull-down resistor enabled high-Z high-Z Isolate mode (VCC = off, VCC(I/O) = on) not present powered high-Z high-Z drive LOW high-Z
VCC, VREG VCC(I/O) DP DM RCV RESET_N, SDA, SCL, ADR/PSW, SE0/VM, DAT/VP, INT_N, OE_N/INT_N, SERVICE_N SPKR_R/MIC, SPKR_L, ID, VBUS, CR_INT, C_A, C_B
high-Z
high-Z
8.2 USB modes
The two USB modes of the ISP1302 are:
* VP_VM bidirectional mode * DAT_SE0 bidirectional mode
In VP_VM USB mode, pin DAT/VP is used for the VP function, pin SE0/VM is used for the VM function, and pin RCV is used for the RCV function. In DAT_SE0 USB mode, pin DAT/VP is used for the DAT function, pin SE0/VM is used for the SE0 function, and pin RCV is not used. Table 12 specifies the functionality of the device during the two USB modes.
Table 12. USB USB functional modes: I/O values Bit DAT_SE0 VP_VM DAT_SE0 0 1 Pin OE_N/INT_N LOW HIGH LOW HIGH
[1] [2] [3] [4] [5] [6] [7]
mode[1]
DAT/VP TxD+[2] RxD+[3] TxD[4] RxD[6]
SE0/VM TxD-[2] RxD-[3] FSE0[5] RSE0[7]
RCV RxD[6] RxD[6] RxD[6] RxD[6]
Some of the modes and signals are provided to achieve backward compatibility with IP cores. TxD+ and TxD- are single-ended inputs to drive the DP and DM outputs, respectively, in single-ended mode. RxD+ and RxD- are the outputs of the single-ended receivers connected to DP and DM, respectively. TxD is the input to drive DP and DM in DAT_SE0 mode. FSE0 is to force an SE0 on the DP and DM lines in DAT_SE0 mode. RxD is the output of the differential receiver. RSE0 is an output, indicating that an SE0 is received on the DP and DM lines.
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8.3 Transparent modes
8.3.1 Transparent UART mode
When in transparent UART mode, an SoC (with the UART controller) communicates through the ISP1302 to another UART device that is connected to its DP and DM lines. The ISP1302 operates as a logic level translator between the following pins:
* For the TxD signal: from SE0/VM (VCC(I/O) level) to DM (VREG level). * For the RxD signal: from DP (VREG level) to DAT/VP (VCC(I/O) level).
The ISP1302 is in transparent UART mode, if bit UART_EN of the Mode Control 1 register is set.
8.3.2 Transparent audio mode
In transparent audio mode, the ISP1302 will disable its DP and DM driver. The carkit interrupt detector is enabled. Built-in analog switches, DC biasing circuits, and the data-during-audio feature can be enabled by setting corresponding bits in the Carkit Control register:
* Stereo mode: SPKR_L on DM and SPKR_R on DP. * Mono and MIC mode: SPKR_L on DM and MIC on DP.
The ISP1302 is in transparent audio mode if bit UART_EN of the Mode Control 1 register is cleared, bit AUDIO_EN of the Mode Control 2 register is set, and bit TRANSP_EN of the Mode Control 1 register is cleared.
8.3.3 Transparent general-purpose buffer mode
In transparent general-purpose buffer mode, the DAT/VP and SE0/VM pins are connected to the DP and DM pins, respectively. The direction of the data transfer can be controlled using bits TRANSP_BDIR1 and TRANSP_BDIR0 of the Mode Control 2 register as specified in Table 14. The ISP1302 is in transparent general-purpose buffer mode, if bit UART_EN = 0, bit AUDIO_EN = 0, bit DAT_SE0 = 1 and bit TRANSP_EN = 1.
8.3.4 Data-during-audio mode
This mode is a combination of audio mode and UART mode. The SPKR_R, SPKR_L and MIC audio signals will be bypassed through the DP and DM lines. UART data bytes can be transmitted or received on the DP and DM lines when the audio signal is running. To transmit data, if the SE0/VM input changes level (either from HIGH to LOW or from LOW to HIGH), a HIGH pulse will be generated on the DM line. The pulse voltage is above 2.9 V. The pulse width is between 200 ns and 500 ns. The data-during-audio transmitting is enabled when the ISP1302 is in transparent audio mode and bit TX_PULSE_EN = 1. To receive data, if a LOW pulse is detected on the DP line, the ISP1302 will toggle the level on the DAT/VP pin. The data-during-audio receiving is enabled when the ISP1302 is in transparent audio mode and bit RX_PULSE_EN = 1. Table 13 provides a summary of device operating modes.
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Table 13. Mode USB mode
Summary of device operating modes Bit UART_EN 0 AUDIO_EN 0 0 TRANSP_EN DAT_SE0 0 1 X 1 USB ATX enabled USB ATX disabled. SE0/VM DM DAT/VP DP see Table 14 Description
Transparent general-purpose 0 buffer mode
Transparent audio mode
0
1
0
X
USB ATX disabled. SPKR_L DM SPKR_R/MIC DP
Transparent UART mode
1
X
X
X
USB ATX disabled. SE0/VM DM DAT/VP DP
Table 14. 00 01 10 11
Transparent general-purpose buffer mode Direction of the data flow DAT/VP DP DAT/VP DP DAT/VP DP DAT/VP DP SE0/VM DM SE0/VM DM SE0/VM DM SE0/VM DM
Bit TRANSP_BDIR[1:0]
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9. Serial controller
9.1 Register map
Table 15 provides an overview of serial controller registers.
Table 15. Register Vendor ID Product ID Version ID Mode Control 1 Mode Control 2 Audio Control OTG Control Misc Control Carkit Control Transmit Positive Width Transmit Negative Width Receive Polarity Recovery Carkit Interrupt Delay OTG Status Interrupt Source Interrupt Latch Interrupt Enable Low Interrupt Enable High Register overview Width (bits) 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Access Memory address[1] R R R R/S/C R/S/C R/S/C R/S/C R/S/C R/S/C R/W R/W R/W R/W R R R/S/C R/S/C R/S/C 00h to 01h 02h to 03h 14h to 15h Set -- 04h Clear -- 05h Set -- 12h Clear -- 13h Set -- 16h Clear -- 17h Set -- 06h Clear -- 07h Set -- 18h Clear -- 19h Set -- 1Ah Clear -- 1Bh 1Ch 1Dh 1Eh 1Fh 10h 08h Set -- 0Ah Clear -- 0Bh Set -- 0Ch Clear -- 0Dh Set -- 0Eh Clear -- 0Fh
[1] The R/W/S/C access type represents a field that can be read, written, set or cleared (set to 0). A register can be read from either of the set or clear addresses. Writing to a write address indicates that values will be directly written to the register. Writing logic 1 to a set address sets the associated bit. Writing logic 1 to a clear address clears the associated bit. Writing logic 0 to either a set or clear address has no effect.
Functionality device identification registers
Reference Section 9.1.1 on page 22
Section 9.1.2 on page 23 control and status registers
interrupt registers
Section 9.1.3 on page 29
9.1.1 Device identification registers
9.1.1.1 Vendor ID register Table 16 provides the bit description of the Vendor ID register.
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Table 16. Bit 15 to 0
Vendor ID register (address R = 00h to 01h) bit description Symbol VENDORID[15:0] Access R Value 04CCh Description NXP Semiconductors' Vendor ID
9.1.1.2
Product ID register The bit description of the Product ID register is given in Table 17.
Table 17. Bit 15 to 0
Product ID register (address R = 02h to 03h) bit description Symbol Access Value 1302h Description Product ID of the ISP1302 PRODUCTID[15:0] R
9.1.1.3
Version ID register Table 18 shows the bit allocation of the register.
Table 18. Bit Symbol Reset Access Bit Symbol Reset Access
[1]
Version ID register (address R = 14h to 15h) bit allocation 15 14 13 12 X[1] R 7 R 6 R 5 R 4 X[1] R R R R R R R R R 3 R 2 R 1 R 0 11 10 9 8 PACKAGEID[3:0] LEGACYID[3:0]
MAJORID[3:0]
MINORID[3:0]
The reset value depends on the version number of the chip.
Table 19. Bit
Version ID register (address R = 14h to 15h) bit description Symbol Description Package information: 0 -- HVQFN24 1 -- WLCSP25
15 to 12 PACKAGEID[3:0]
11 to 8
LEGACYID[3:0]
Legacy version ID: 0 -- New method of defining the version ID 1 to 15 -- Legacy method of defining the version ID
7 to 4 3 to 0
MAJORID[3:0] MINORID[3:0]
Version ID, major number; this number starts with 1 and increments by 1 if there is a major update to the chip. Version ID, minor number; this number starts with 0 and increments by 1 if there is a minor update to the chip.
9.1.2 Control registers
9.1.2.1 Mode Control 1 register The bit allocation of the Mode Control 1 register is given in Table 20.
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Table 20. Bit Symbol Reset Access
Mode Control 1 register (address S = 04h, C = 05h) bit allocation 7 reserved 0 R/S/C 6 UART_EN 0/1 R/S/C Table 21. Bit 7 6 UART_EN 5 OE_INT_ EN 0 R/S/C 4 BDIS_ ACON_EN 0 R/S/C 3 TRANSP_ EN 0 R/S/C 2 DAT_SE0 0 R/S/C 1 SUSPEND 0 R/S/C 0 SPEED 0 R/S/C
Mode Control 1 register (address S = 04h, C = 05h) bit description Description reserved When set, the ATX is in transparent UART mode. The default value of this bit depends on the SERVICE_N pin. On reset, if SERVICE_N = HIGH, the reset value of UART_EN = 0; if SERVICE_N = LOW, the reset value of UART_EN = 1. When set and when in suspend mode, pin OE_N/INT_N becomes an output and is asserted when an interrupt occurs.
Symbol
5 4
OE_INT_EN
BDIS_ACON_ This bit has two functions: EN For an A-device, this bit works as BDIS_ACON_EN. It enables the A-device to connect if the B-device disconnect is detected; see Section 7.10. 0 -- DP pull-up resistor is controlled by the DP_PULLUP bit in the OTG Control register. 1 -- DP pull-up resistor will connect on the B-device disconnect. For a B-device, this bit works as ACON_BSE0_EN. It enables the B-device to drive SE0 on DP and DM, if the A-device connect is detected. 0 -- B-device will stop driving SE0. 1 -- B-device will start to drive SE0, if the A-device connect is detected.
3 2 1
TRANSP_EN DAT_SE0 SUSPEND
When set, the ATX is in transparent general-purpose buffer mode. 0 -- VP_VM mode 1 -- DAT_SE0 mode Sets the transceiver in low-power mode. 0 -- Active-power mode 1 -- Low-power mode (differential receiver is disabled if SPEED = 1)
0
SPEED
Set the rise time and the fall time of the transmit driver in USB modes. 0 -- Low-speed mode 1 -- Full-speed mode
9.1.2.2
Mode Control 2 register For the bit allocation of this register, see Table 22.
Table 22. Bit Symbol Reset Access
Mode Control 2 register (address S = 12h, C = 13h) bit allocation 7 reserved 0 R/S/C 6 PSW_OE 0 R/S/C 5 AUDIO_EN 0 R/S/C 4 TRANSP_ BDIR1 0 R/S/C 3 TRANSP_ BDIR0 0 R/S/C 1 R/S/C 2 reserved 0 R/S/C 1 0 PWR_DN 0 R/S/C
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Mode Control 2 register (address S = 12h, C = 13h) bit description Symbol PSW_OE AUDIO_EN Description reserved 0 -- ADR/PSW pin acts as an input. 1 -- ADR/PSW pin is driven. Enables the ISP1302 in carkit audio mode. 0 -- Audio mode disable: DP_INT detector is turned off, and single-ended receivers are turned on. 1 -- Audio mode enable: DP_INT detector is turned on, and single-ended receivers are turned off.
Table 23. Bit 7 6 5
4 to 3 2 to 1 0
TRANSP_BDIR Controls the direction of data transfer in transparent general-purpose [1:0] buffer mode; see Table 14 PWR_DN reserved Set to power-down mode; activities on pin SCL or the interrupt event can wake-up the chip; see Section 10
9.1.2.3
Audio Control register Table 24 provides the bit allocation of the register.
Table 24. Bit Symbol Reset Access
Audio Control register (address S = 16h, C = 17h) bit allocation 7 PH_ID_ ACK 0 R/S/C 6 PH_ID_INT 0 R/S/C Table 25. Bit 7 6 0 R/S/C 0 R/S/C 5 4 reserved 0 R/S/C 0 R/S/C 3 2 1 SW_MIC_ SPKR_L 0 R/S/C 0 reserved 0 R/S/C
Audio Control register (address S = 16h, C = 17h) bit description Description If set, wait for time tPH_ID_WT, turn on the ID pull-down switch for tPH_ID_INT, then turn off. Bit PH_ID_ACK autoclears to 0. See Table 4. If set, turn on the ID pull-down switch for time tPH_ID_INT and then turn off. Bit PH_ID_INT autoclears to 0. See Table 4. reserved
Symbol PH_ID_ACK PH_ID_INT
5 to 2 1
SW_MIC_SPKR_ Audio loopback test: L 0 -- Turn off the switch between the SPKR_R/MIC and SPKR_L pins. 1 -- Turn on the switch between the SPKR_R/MIC and SPKR_L pins. reserved
0
9.1.2.4
OTG Control register Table 26 shows the bit allocation of the OTG Control register.
Table 26. Bit Symbol Reset Access
ISP1302_1
OTG Control register (address S = 06h, C = 07h) bit allocation 7 VBUS_ CHRG 0 R/S/C 6 VBUS_ DISCHRG 0 R/S/C 5 VBUS_ DRV 0 R/S/C 4 ID_PULL DN 0 R/S/C 3 DM_PULL DOWN 1 R/S/C 2 DP_PULL DOWN 1 R/S/C 1 DM_PULL UP 0 R/S/C 0 DP_PULL UP 0 R/S/C
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OTG Control register (address S = 06h, C = 07h) bit description Description Charge VBUS through a pull-up resistor (RUP(VBUS)), which is connected to VREG. 0 -- Disconnect the resistor 1 -- Connect the resistor
Table 27. Bit 7
Symbol VBUS_CHRG
6
VBUS_DISCHRG
Discharge VBUS through a pull-down resistor (RDN(VBUS)). 0 -- Disconnect the resistor 1 -- Connect the resistor
5
VBUS_DRV
Drive VBUS to 5 V through the charge pump. 0 -- Charge pump is disabled 1 -- Charge pump is enabled
4
ID_PULLDN
Connect pin ID to ground. See Table 5. 0 -- Disconnected 1 -- Connected
3
DM_PULLDOWN
Connect the DM pull-down resistor (RDN(DM)). 0 -- DM pull-down resistor is disconnected 1 -- DM pull-down resistor is connected
2
DP_PULLDOWN
Connect the DP pull-down resistor (RDN(DP)). 0 -- DP pull-down resistor is disconnected 1 -- DP pull-down resistor is connected
1
DM_PULLUP
Connect the DM pull-up resistor (RUP(DM)). 0 -- DM pull-up resistor is disconnected 1 -- DM pull-up resistor is connected
0
DP_PULLUP
Connect the DP pull-up resistor (RUP(DP)). 0 -- DP pull-up resistor is disconnected (assuming that bit BDIS_ACON_EN is logic 0) 1 -- DP pull-up resistor is connected
9.1.2.5
Misc Control register Table 28 shows the bit allocation of the register.
Table 28. Bit Symbol Reset Access
Misc Control register (address S = 18h, C = 19h) bit allocation 7 FORCE_ DP_HIGH 0 R/S/C 6 FORCE_ DP_LOW 0 R/S/C Table 29. Bit 7 6 5 5 reserved 0 R/S/C 4 UART_2V8 _EN 1 R/S/C 3 IDPU_DIS 0 R/S/C 2 DP_WKPU _EN 0 R/S/C 1 SRP_INIT 0 R/S/C 0 REG_BY PASS_DIS 0 R/S/C
Misc Control register (address S = 18h, C = 19h) bit description Description Forces the DP pin to be driven to LOW reserved
Symbol FORCE_DP_LOW -
FORCE_DP_HIGH Forces the DP pin to be driven to HIGH
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Misc Control register (address S = 18h, C = 19h) bit description ...continued Description This bit indicates the output voltage level of the internal regulator. This bit is only valid when bit UART_EN is logic 1. When this bit and bit UART_EN are logic 1, the internal regulator bypass switch will always be disabled, ignoring the value of bit REG_BYPASS_DIS. This is to ensure that the internal regulator outputs +2.8 V, when VCC is 3.0 V to 4.5 V. 0 -- Internal regulator outputs 3.3 V 1 -- Internal regulator outputs 2.8 V
Table 29. Bit 4
Symbol UART_2V8_EN
3 2
IDPU_DIS DP_WKPU_EN
0 -- Internal ID pin pull-up resistor is enabled 1 -- Internal ID pin pull-up resistor is disabled This bit will enable RweakUP(DP) on the DP line. It is provided to support the detection of external accessory devices. This bit is optional. 0 -- Disconnect the DP weak pull-up resistor (RweakUP(DP)) 1 -- Connect the DP weak pull-up resistor (RweakUP(DP))
1
SRP_INIT
0 -- No event 1 -- Initialize SRP, if this bit is set, the following events occur in sequence: enable DP pull-up for 7.5 ms, enable the VBUS_CHRG resistor for 32 ms, enable the VBUS_DISCHRG resistor for 13 ms. This bit will autoclear when the sequence is complete.
0
REG_BYPASS_ DIS
0 -- Internal regulator bypass switch is turned on, when VCC < 3.6 V 1 -- Internal regulator bypass switch is turned off
9.1.2.6
Carkit Control register Table 30 shows the bit allocation of this register.
Table 30. Bit Symbol
Carkit Control register (address S = 1Ah, C = 1Bh) bit allocation 7 reserved 6 5 SPKR_MIC _EN 0 R/S/C Table 31. Bit 7 to 6 5 4 3 2 1 0 0 R/S/C 4 SPKR_L_ EN 0 R/S/C 3 SPKR_R_ BIAS_EN 0 R/S/C 2 SPKR_L_ BIAS_EN 0 R/S/C 1 RX_ PULSE_E N 0 R/S/C 0 TX_PULSE _EN 0 R/S/C
Reset Access
0 R/S/C
Carkit Control register (address S = 1Ah, C = 1Bh) bit description Symbol SPKR_MIC_EN SPKR_L_EN SPKR_R_BIAS_EN SPKR_L_BIAS_EN RX_PULSE_EN TX_PULSE_EN Description reserved Enables the speaker right or MIC line switch Enables the speaker left line switch Enables the DC bias for the speaker right line Enables the DC bias for the speaker left line Enables the data-during-audio receive Enables the data-during-audio transmit
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9.1.2.7
Transmit Positive Width register This register specifies the width of the positive pulse, that is, the output on the DM line when the TX_PULSE_EN bit is set. The time is measured in units of 60 MHz clock periods. The clock has a frequency in the range of fclk(dda). For bit description, see Table 32.
Table 32. Transmit Positive Width register (address R/W = 1Ch) bit description Legend: * reset value Bit 7 to 0 Symbol TXPOSIWIDTH[7:0] Access R/W Value 15h* Description Transmit positive pulse width
9.1.2.8
Transmit Negative Width register This register specifies the width of the negative pulse, that is, the output on the DM line when the TX_PULSE_EN bit is set. The time is measured in units of 60 MHz clock periods. The clock has a frequency in the range of fclk(dda). For the bit description, see Table 33.
Table 33. Transmit Negative Width register (address R/W = 1Dh) bit description Legend: * reset value Bit 7 to 0 Symbol TXNEGWIDTH[7:0] Access R/W Value 2Ah* Description Transmit negative pulse width
9.1.2.9
Receive Polarity Recovery register The bit description of the register is shown in Table 34.
Table 34. Receive Polarity Recovery register (address R/W = 1Eh) bit description Legend: * reset value Bit Symbol Access R/W Value 64h* Description Sets the RxD polarity recovery time in units of 0.25 ms. The timer tolerance is dictated by fclk(dda). Valid when bit RX_PULSE_EN is set. 7 to 0 RX_RECOVERY[7:0]
9.1.2.10
Carkit Interrupt Delay register The bit description of the register is given in Table 35.
Table 35. Carkit Interrupt Delay register (address R/W = 1Fh) bit description Legend: * reset value Bit 7 to 0 Symbol CR_INT_DELAY[7:0] Access R/W Value C8h* Description Sets the carkit interrupt detection time in units of 0.25 ms. The timer tolerance is dictated by fclk(dda).
9.1.2.11
OTG Status register Table 36 shows the bit allocation of the OTG Status register.
Table 36. Bit Symbol Reset Access
[1]
OTG Status register (address R = 10h) bit allocation 7 reserved 0 R 6 B_SESS_ END -[1] R 0 R 5 reserved 0 R 4 3 ID_102K -[1] R 2 ID_440K -[1] R 1 ID_200K -[1] R 0 reserved 0 R
The reset value depends on the status of the respective pin.
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OTG Status register (address R = 10h) bit description Description reserved Set when the VBUS voltage is below the B-device session end threshold (0.2 V to 0.8 V). In power-down mode, this bit is fixed as logic 0. reserved Indicates that pin ID is connected to ground through RDN(ID) = 102 k. This bit indicates that the phone accessory is connected. For details, refer to USB Carkit Specification (CEA-936-A). In power-down mode, this bit is fixed as logic 0. Indicates that pin ID is connected to ground through RDN(ID) = 440 k. This bit indicates the default current capability of the connected charger. For details, refer to USB Carkit Specification (CEA-936-A). In power-down mode, this bit is fixed as logic 0. Indicates that pin ID is connected to ground through RDN(ID) = 200 k. This bit indicates the default current capability of the connected charger. For details, refer to USB Carkit Specification (CEA-936-A). In power-down mode, this bit is fixed as logic 0. reserved
Table 37. Bit 7 6 -
Symbol B_SESS_END
5 to 4 3
ID_102K
2
ID_440K
1
ID_200K
0
-
9.1.3 Interrupt registers
9.1.3.1 Interrupt Source register Table 38 shows the bit allocation of this register that indicates the current state of the signals that can generate an interrupt.
Table 38. Bit Symbol Reset Access
[1]
Interrupt Source register (address R = 08h) bit allocation 7 DP_INT -[1] R 6 BDIS_ ACON 0 R 5 ID_FLOAT -[1] R 4 DM_HI -[1] R 3 ID_GND -[1] R 2 DP_HI -[1] R 1 0 SESS_VLD VBUS_VLD -[1] R -[1] R
The reset value depends on the status of the respective pin.
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ISP1302
USB OTG transceiver with carkit support
Interrupt Source register (address R = 08h) bit description Description This bit has two functions: When the Carkit Interrupt Delay register is 0h and the voltage on the CR_INT pin is below the carkit interrupt threshold (0.4 V to 0.6 V), this bit is set. 0 -- Voltage on the CR_INT pin is above the carkit interrupt threshold (0.4 V to 0.6 V). 1 -- Voltage on the CR_INT pin is below the carkit interrupt threshold (0.4 V to 0.6 V). When the Carkit Interrupt Delay register is nonzero and the voltage on the CR_INT pin is below the carkit interrupt threshold (0.4 V to 0.6 V) for a period of time defined in the Carkit Interrupt Delay register, this bit is set. 0 -- No event 1 -- The carkit stereo interrupt event is detected. In power-down mode, this bit is fixed as logic 0.
Table 39. Bit 7
Symbol DP_INT
6
BDIS_ACON
Set when bit BDIS_ACON_EN is set, and the ISP1302 enables the DP pull-up resistor after detecting the B-device disconnect (SE0). 0 -- No event 1 -- BDIS_ACON is detected.
5
ID_FLOAT
Indicates the status of pin ID. 0 -- ID pin is not floating. 1 -- ID pin is floating.
4
DM_HI
DM single-ended receiver output. 0 -- LOW 1 -- HIGH
3
ID_GND
Indicates the status of pin ID: 0 -- ID pin is not grounded. 1 -- ID pin is grounded. In power-down mode, this bit is fixed as logic 0.
2
DP_HI
DP single-ended receiver output. 0 -- LOW 1 -- HIGH
1
SESS_VLD
VBUS session valid detector. 0 -- VBUS is lower than VA_SESS_VLD (bit ID_GND = 1) or VB_SESS_VLD (bit ID_GND = 0). 1 -- VBUS is higher than VA_SESS_VLD (bit ID_GND = 1) or VB_SESS_VLD (bit ID_GND = 0).
0
VBUS_VLD
This bit has two functions: For the A-device (bit ID_GND = 1), it acts as the VBUS valid detector. 0 -- VBUS is lower than the VBUS valid threshold. 1 -- VBUS is higher than the VBUS valid threshold. For the B-device (bit ID_GND = 0), it acts as B_SESS_END (B-device session end detector). 0 -- VBUS is above the B-device session end threshold (0.2 V to 0.8 V). 1 -- VBUS is below the B-device session end threshold (0.2 V to 0.8 V). In power-down mode, this bit is fixed as logic 0.
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9.1.3.2
Interrupt Latch register This register indicates the source that generates an interrupt. For the bit allocation, see Table 40.
Table 40. Bit Symbol Reset Access
Interrupt Latch register (address S = 0Ah, C = 0Bh) bit allocation 7 DP_INT_ INT 0 R/S/C 6 BDIS_ ACON_INT 0 R/S/C Table 41. Bit 7 6 5 4 3 2 1 0 5 ID_FLOAT_ INT 0 R/S/C 4 DM_HI_ INT 0 R/S/C 3 ID_GND_ INT 0 R/S/C 2 1 0 VBUS_ VLD_INT 0 R/S/C DP_HI_INT SESS_VLD _INT 0 R/S/C 0 R/S/C
Interrupt Latch register (address S = 0Ah, C = 0Bh) bit description Symbol DP_INT_INT Description 0 -- No interrupt 1 -- Interrupt on the DP_INT status change BDIS_ACON_INT 0 -- No interrupt 1 -- Interrupt on the BDIS_ACON status change ID_FLOAT_INT DM_HI_INT ID_GND_INT DP_HI_INT SESS_VLD_INT VBUS_VLD_INT 0 -- No interrupt 1 -- Interrupt on the ID_FLOAT status change 0 -- No interrupt 1 -- Interrupt on the DM_HI status change 0 -- No interrupt 1 -- Interrupt on the ID_GND status change 0 -- No interrupt 1 -- Interrupt on the DP_HI status change 0 -- No interrupt 1 -- Interrupt on the SESS_VLD status change 0 -- No interrupt 1 -- Interrupt on the VBUS_VLD status change
9.1.3.3
Interrupt Enable Low register The bits in this register enable interrupts when the corresponding bits in the Interrupt Source register change from logic 1 to logic 0. Table 42 shows the bit allocation of the register.
Table 42. Bit Symbol Reset Access
Interrupt Enable Low register (address S = 0Ch, C = 0Dh) bit allocation 7 DP_INT_ IEL 0 R/S/C 6 reserved 0 R/S/C 5 ID_FLOAT _IEL 0 R/S/C 4 DM_HI_IEL 0 R/S/C 3 ID_GND_ IEL 0 R/S/C 2 DP_HI_IEL 0 R/S/C 1 SESS_VLD _IEL 0 R/S/C 0 VBUS_ VLD_IEL 0 R/S/C
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Interrupt Enable Low register (address S = 0Ch, C = 0Dh) bit description Symbol DP_INT_IEL ID_FLOAT_IEL DM_HI_IEL ID_GND_IEL DP_HI_IEL SESS_VLD_IEL VBUS_VLD_IEL Description 0 -- Disable 1 -- Enable reserved 0 -- Disable 1 -- Enable 0 -- Disable 1 -- Enable 0 -- Disable 1 -- Enable 0 -- Disable 1 -- Enable 0 -- Disable 1 -- Enable 0 -- Disable 1 -- Enable
Table 43. Bit 7 6 5 4 3 2 1 0
9.1.3.4
Interrupt Enable High register The bits in this register enable interrupts when the corresponding bits in the Interrupt Source register change from logic 0 to logic 1. For the bit allocation, see Table 44.
Table 44. Bit Symbol Reset Access
Interrupt Enable High register (address S = 0Eh, C = 0Fh) bit allocation 7 DP_INT_ IEH 0 R/S/C 6 5 4 DM_HI_ IEH 0 R/S/C 3 ID_GND_ IEH 0 R/S/C 2 1 0 VBUS_ VLD_IEH 0 R/S/C BDIS_ ID_FLOAT_ ACON_IEH IEH 0 R/S/C Table 45. Bit 7 6 5 4 3 0 R/S/C DP_HI_IEH SESS_VLD _IEH 0 R/S/C 0 R/S/C
Interrupt Enable High register (address S = 0Eh, C = 0Fh) bit description Symbol DP_INT_IEH Description 0 -- Disable 1 -- Enable BDIS_ACON_IEH 0 -- Disable 1 -- Enable ID_FLOAT_IEH DM_HI_IEH ID_GND_IEH 0 -- Disable 1 -- Enable 0 -- Disable 1 -- Enable 0 -- Disable 1 -- Enable
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Interrupt Enable High register (address S = 0Eh, C = 0Fh) bit description Symbol DP_HI_IEH SESS_VLD_IEH VBUS_VLD_IEH Description 0 -- Disable 1 -- Enable 0 -- Disable 1 -- Enable 0 -- Disable 1 -- Enable
Table 45. Bit 2 1 0
9.2 Interrupts
Any of the Interrupt Source register signals given in Table 38 can generate an interrupt, when the signal becomes either LOW or HIGH. After an interrupt is generated, the SoC should be able to read the status of each signal and the bit that indicates whether that signal generated the interrupt. A bit in the Interrupt Latch register is set when any of the following events occurs:
* Writing logic 1 to a set address sets the corresponding bit. * The corresponding bit in the Interrupt Enable High register is set, and the associated
signal changes from LOW to HIGH.
* The corresponding bit in the Interrupt Enable Low register is set, and the associated
signal changes from HIGH to LOW.
* The INT_N pin will be asserted if one or more bits in the Interrupt Latch register are
set. The INT_N pin will be de-asserted if all the bits in the Interrupt Latch register are cleared by software.
9.3 I2C-bus protocol
For detailed information, refer to The I2C-bus specification; ver. 2.1.
9.3.1 I2C-bus byte transfer format
Table 46. S[1] I2C-bus byte transfer format Byte 1 8 bits
[1] [2] [3] S = Start. A = Acknowledge. P = Stop.
A[2]
Byte 2 8 bits
A[2]
Byte 3 8 bits
A[2]
.. ..
A[2]
P[3]
9.3.2 I2C-bus device address
Table 47. Bit Symbol Value
[1]
I2C-bus slave address bit allocation 7 A6 0 6 A5 1 5 A4 0 4 A3 1 3 A2 1 2 A1 0 1 A0
[1]
0 R/W X
Determined by the status of the ADR/PSW pin on the rising edge of RESET_N. If ADR/PSW = HIGH, bit A0 = 1; if ADR/PSW = LOW, bit A0 = 0. Bit A0 will be zero if there is no hardware reset pulse on the RESET_N pin after power on.
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I2C-bus slave address bit description Symbol A[6:0] R/W Description Device Address: The device address of the ISP1302 is 01 0110 (A0), where A0 is determined by pin ADR/PSW. Read or write command. 0 -- Write 1 -- Read
Table 48. Bit 7 to 1 0
9.3.3 Write format
A write operation can be performed as:
* One-byte write to the specified register address. * Multiple-byte write to N consecutive registers, starting from the specified start
address. N defines the number of registers to write. If N = 1, only the start register is written. 9.3.3.1 One-byte write Table 49 describes the transfer format for a one-byte write.
Table 49. Byte S Device select ACK Register address K ACK Write data K ACK P Transfer format description for a one-byte write Description master starts with a START condition master transmits the device address and write command bit R/W = 0 slave generates an acknowledgment master transmits the address of register K slave generates an acknowledgment master writes data to register K slave generates an acknowledgment master generates a STOP condition
9.3.3.2
Multiple-byte write Table 50 describes the transfer format for multiple-byte write.
Table 50. Byte S Device select ACK Register address K Transfer format description for a multiple-byte write Description master starts with a START condition master transmits the device address and write command bit R/W = 0 slave generates an acknowledgment master transmits the address of register K. This is the start address for writing multiple data bytes to consecutive registers. After a byte is written, the register address is automatically incremented by 1. Remark: If the master writes to a nonexistent register, the slave must send a 'not ACK' and also must not increment the index address. ACK Write data K ACK Write data K + 1 slave generates an acknowledgment master writes data to register K slave generates an acknowledgment master writes data to register K + 1
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Transfer format description for a multiple-byte write ...continued Description slave generates an acknowledgment :
Table 50. Byte ACK :
Write data K + N - 1 master writes data to register K + N - 1. When the incremented address K + N - 1 becomes > 255, the register address rolls over to 0. Therefore, it is possible that some registers may be overwritten, if the transfer is not stopped before the rollover. ACK P slave generates an acknowledgment master generates a STOP condition
Figure 11 illustrates the write format for a one-byte write and a multiple-byte write.
ACK S device select wr register address K
ACK write data K
ACK P
one-byte write
ACK S device select wr register address K
ACK write data K
ACK write data K + 1
ACK
ACK write data K + 2 write data K + 3
ACK
ACK write data K + N - 1
ACK P
004aaa569
.... maximum, rollover to 0
multiple-byte write
Fig 11. Writing data to the ISP1302 registers
9.3.4 Read format
A read operation can be performed in two ways:
* Current address read: To read the register at the current address.
- Single register read
* Random address read: To read N registers starting at a specified address. N defines
the number of registers to be read. If N = 1, only the start register is read. - Single register read - Multiple register read 9.3.4.1 Current address read The transfer format description for a current address read is given in Table 51. For the illustration, see Figure 12.
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Transfer format description for current address read Description master starts with a START condition master transmits the device address and read command bit R/W = 1 slave generates an acknowledgment slave transmits and master reads data from register K. If the start address is not specified, the read operation starts from where the index register is pointing to because of a previous read or write operation. master terminates the read operation by generating a no acknowledgement master generates a stop condition
Table 51. Byte S
Device select ACK Read data K
No ACK P
ACK S device select rd read data K
no ACK P
004aaa570
current address read
Fig 12. Current address read
9.3.4.2
Random address read: single read Table 52 describes the transfer format for a single-byte read. Figure 13 illustrates the byte sequence.
Table 52. SDA line S Device select ACK Register address K ACK S Device select ACK Read data K No ACK P Transfer format description for a single-byte read Description master starts with a START condition master transmits the device address and write command bit R/W = 0 slave generates an acknowledgment master transmits (start) address of register K from which to be read slave generates an acknowledgment master restarts with a START condition master transmits the device address and read command bit R/W = 1 slave generates an acknowledgment slave transmits and master reads data from register K master terminates the read operation by generating a no acknowledgement master generates a STOP condition
9.3.4.3
Random address read: multiple read The transfer format description for a multiple-byte read is given in Table 53. Figure 13 illustrates the byte sequence.
Table 53. SDA line S Device select ACK Register address K Transfer format description for a multiple-byte read Description master starts with a START condition master transmits the device address and write command bit R/W = 0 slave generates an acknowledgment master transmits (start) address of register K from which to be read
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USB OTG transceiver with carkit support
Transfer format description for a multiple-byte read ...continued Description slave generates an acknowledgment master restarts with a START condition master transmits the device address and read command bit R/W = 1 slave generates an acknowledgment slave transmits and master reads data from register K. After a byte is read, the address is automatically incremented by 1. master generates an acknowledgment slave transmits and master reads data from register K + 1 master generates an acknowledgment :
Table 53. SDA line ACK S
Device select ACK Read data K ACK Read data K + 1 ACK :
Read data K + N - 1 slave transmits and master reads data register K + N - 1. This is the last register to read. After incrementing, the address rolls over to 0. Here, N represents the number of addresses available in the slave. No ACK P master terminates the read operation by generating a no acknowledgement master generates a STOP condition
ACK S device select wr register address K
ACK S device select rd
ACK read data K
no ACK P
random address single read
ACK S device select wr ACK read data K + 1 read data K + 2 register address K
ACK S ACK device select rd
ACK read data K
ACK
ACK write data K + N - 1
no ACK P
004aaa571
.... maximum, rollover to 0
random access multiple read
Fig 13. Random address read
10. Clock wake-up scheme
The following subsections explain the ISP1302 clock stop timing, events triggering the clock to wake up, and the timing of the clock wake-up.
10.1 Power-down event
The internal clock (LazyClock and/or I2C-bus clock) is stopped when bit PWR_DN is set. It takes td(clkstp) for the clock to stop from the time the power-down condition is detected. The clock always stops at its falling edge. The internal clock must be woken up first before any register read or write operation.
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10.2 Clock wake-up event
The clock wakes up when any of the following events occurs on the ISP1302 pins:
* Pin SCL goes LOW. * Pin VBUS goes above the session valid threshold, provided bit SESS_VLD_IEH of the
Interrupt Enable High register is set.
* Status bit ID_FLOAT changes from logic 1 to logic 0, provided bit ID_FLOAT_IEL of
the Interrupt Enable Low register is set.
* Status bit ID_FLOAT changes from logic 0 to logic 1, provided bit ID_FLOAT_IEH of
the Interrupt Enable High register is set.
* DP goes HIGH provided the DP_HI_IEH bit in the Interrupt Enable High register is
set.
* DM goes HIGH provided the DM_HI_IEH bit in the Interrupt Enable High register is
set. The event triggers the clock to start. The clock start-up time is tstartup(lclk). A stable clock is guaranteed after six clock cycles. The clock will always start at its rising edge. When an event is triggered and the clock is started, the clock will remain active for td(clkstp). If bit PWR_DN is not cleared within this period, the clock will stop. If the clock wakes up because of any event other than SCL going LOW, an interrupt will be generated once the clock is active.
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11. Limiting values
Table 54. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Voltage VCC VCC(I/O) VI supply voltage input/output supply voltage input voltage on digital pins ADR/PSW, SERVICE_N and RESET_N on all other digital pins on analog pins DP and DM on analog pins SPKR_L and SPKR_R/MIC VI(VBUS) VI(ID) VESD input voltage on pin VBUS input voltage on pin ID electrostatic discharge voltage ILI < 1 A Human Body Model (JESD22-A114D) Machine Model (JESD22-A115-A) Charge Device Model (JESD22-C101-C) Current Ilu Tstg Tj
[1] [2]
[4]
Conditions
Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -2 -200 -500 -60 -40
Max +5.5[1] +4.6 +4.6 VCC(I/O) + 0.5 +4.6[2] +4.6 +7.0[3] +5.5 +2 +200 +500 100 +125 +125
Unit V V V V V V V V kV V V mA C C
latch-up current storage temperature junction temperature
When the charge pump is enabled, +5.5 V is only allowed for short period of time 1 second.
Temperature
The ISP1302 has been tested according to Universal Serial Bus Specification Rev. 2.0, Section 7.1.1. The DP and DM lines were shorted to VBUS/GND for 24 hours with 50 % transmit/receive duty cycle. The ISP1302 operated normally after this test and is therefore compliant to the requirement. When an external series resistor is added to the VBUS pin, it can withstand higher voltages for longer periods of time because the resistor limits the current flowing into the VBUS pad. For example, with an external 1 k resistor, VBUS can tolerate 10 V for at least 5 seconds. If an external resistor is used, the internal charge pump must never be used, and other OTG functions must be verified in the customer application. Equivalent to discharging a 100 pF capacitor through a 1.5 k resistor (Human Body Model).
[3]
[4]
12. Recommended operating conditions
Table 55. Voltage VCC VCC(I/O) supply voltage input/output supply voltage 3.0 1.4 4.5 3.6[1] V V Recommended operating conditions Conditions Min Typ Max Unit Symbol Parameter
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Table 55. VI
Recommended operating conditions ...continued Conditions digital pins ADR/PSW, SERVICE_N and RESET_N on all other digital pins on analog pins DP and DM on analog pins SPKR_L and SPKR_R/MIC Min 0 0 0 0 1.4 -40 Typ Max 3.6 VCC(I/O) 3.6 3.6 3.6 +85 Unit V V V V V C input voltage
Symbol Parameter
V(pu)OD Tamb
[1]
open-drain pull-up voltage ambient temperature
Temperature
VCC(I/O) should be less than or equal to VCC.
13. Static characteristics
Table 56. Static characteristics: supply pins VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Voltage VO(VREG) output voltage on pin VREG bit UART_2V8_EN = 0; Iload 300 A[1] bit UART_2V8_EN = 1 and bit UART_EN = 1; Iload 10 mA VPOR(trip) Current ICC supply current transmitting and receiving at 12 Mbit/s; CL = 50 pF on pins DP and DM transmitting and receiving at 12 Mbit/s
[3]
Parameter
Conditions
Min 3.0[2] 2.35 1.5 -
Typ 5
Max 3.6 2.85 2.5 8
Unit V V V mA
power-on reset trip voltage
ICC(I/O) ICC(I/O)(isol) ICC(idle) ICC(I/O)(stat) ICC(stat)
supply current on pin VCC(I/O)
[3]
-
1 0.5 12
2 10 1 20 25
mA A mA A A
isolate mode supply current on VCC not connected pin VCC(I/O) idle and SE0 supply current static supply current on pin VCC(I/O) static supply current idle: VDP > 2.7 V, VDM < 0.3 V; SE0: VDP < 0.3 V, VDM < 0.3 V idle, SE0 or suspend bit PWR_DN = 1, bit SUSPEND = 1 or VCC(I/O) = 0 V
[4] [4]
-
[1] [2] [3] [4]
Iload includes the DP pull-up resistor current. In power-down mode, the minimum voltage is 2.7 V. Maximum value characterized only, not tested in production. Excluding any load current to the 1.5 k and 15 k pull-up and pull-down resistors (200 A typical).
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Table 57. Static characteristics: digital pins VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol VIL VIH VOL VOH Parameter LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage IOL = 2 mA IOL = 100 A IOH = 2 mA IOH = 100 A Leakage current ILI IOZ Capacitance Cin
[1]
[1]
Conditions
Min 0.7VCC(I/O) VCC(I/O) - 0.4 VCC(I/O) - 0.15 -1 -5
Typ -
Max 0.3VCC(I/O) 0.4 0.15 +1 +5 10
Unit V V V V V V A A pF
Input level voltage
Output level voltage
input leakage current off-state output current input capacitance
Not applicable for open-drain outputs.
Open-drain output current
pin to ground
-
Table 58. Static characteristics: analog I/O pins DP and DM VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol VDI VCM VIL VIH VOL VOH Voltage Vth(DP)L VTERM ILZ Capacitance Cin Resistance RDN(DP) RDN(DM) pull-down resistance on pin DP pull-down resistance on pin DM 14.25 14.25 24.8 24.8 k k input capacitance pin to AGND 10 pF DP LOW threshold voltage termination voltage off-state leakage current
[1]
Parameter differential input sensitivity differential common mode voltage range LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage
Conditions |VDP - VDM| includes VDI range
Min 0.2 0.8 2.0
Typ -
Max 2.35 0.8 0.3 3.6 0.6 3.6 +1
Unit V V V V V V V V A
Input level voltage
Output level voltage RL of 1.5 k to +3.6 V RL of 15 k to ground 2.8 0.4 3.0 -1
Leakage current
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Table 58. Static characteristics: analog I/O pins DP and DM ...continued VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol RUP(DP) RweakUP(DP) ZDRV ZINP
[1] [2]
Parameter pull-up resistance on pin DP weak pull-up resistance on pin DP driver output impedance input impedance
Conditions bus idle bus driven steady-state drive
[2]
Min 900 1425 105 34 1
Typ 150 -
Max 1575 3090 195 44 -
Unit k M
For the upstream port pull-up resistance (RPU). Includes external series resistances of 33 5 % each on DP and DM.
Table 59. Static characteristics: analog I/O pin ID VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Resistance RUP(int)(ID) RDN(ID) internal pull-up resistance on pin ID pull-down resistance on bit ID_PULLDOWN = 1; output pin ID pull-down resistance bit ID_102K = 1; external 102 k pull-down resistance bit ID_200K = 1; external 200 k pull-down resistance bit ID_440K = 1; external 440 k pull-down resistance bit ID_FLOAT = 1; external pull-down resistance on pin ID for mini-B plug bit ID_GND = 1; external pull-down resistance on pin ID for mini-A plug 70 101 198 436 105 102 200 440 130 50 103 202 444 k k k k k Parameter Conditions Min Typ Max Unit
-
-
10
Table 60. Static characteristics: charge pump VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Current Iload Voltage VO(VBUS) VL(VBUS) VA_VBUS_VLD output voltage on pin VBUS leakage voltage on pin VBUS A-device VBUS valid voltage Iload = 50 mA; Cext = 220 nF charge pump disabled 4.4 4.4 5 5.25 0.2 4.7 V V V load current Cext = 220 nF; VBUS > VA_VBUS_VLD 50 mA Parameter Conditions Min Typ Max Unit
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Table 60. Static characteristics: charge pump ...continued VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol VB_SESS_END VA_SESS_VLD VB_SESS_VLD Vhys(A_SESS_VLD) Vhys(B_SESS_VLD) cp Resistance RUP(VBUS) RDN(VBUS) RI(idle)(VBUS) pull-up resistance on pin VBUS pull-down resistance on pin VBUS idle input resistance on pin VBUS connect to VREG when bit VBUS_CHRG = 1 connect to ground when bit VBUS_DISCHRG = 1 bit ID_GND = 1 and bit VBUS_DRV = 0 bit ID_GND = 0, bit VBUS_DRV = 1, or VCC and VCC(I/O) are not powered Capacitance Cext external capacitance Iload = 8 mA Iload = 20 mA Iload = 25 mA Iload = 50 mA
[1] Efficiency when loaded.
Parameter B-device session end voltage A-device session valid voltage B-device session valid voltage A-device session valid hysteresis voltage B-device session valid hysteresis voltage charge pump efficiency
Conditions
Min 0.2
Typ 80 80 75 70 200
Max 0.8 2.0 4.0 1000 1200 100 270
Unit V V V mV mV % k k
bit ID_GND = 1 bit ID_GND = 0
0.8 0.8 -
Iload = 50 mA; VCC = 3 V
[1]
460 660 52.5 130
20 61 90 198
-
-
nF nF nF nF
Table 61. Static characteristics: analog I/O pins SPKR_R/MIC and SPKR_L VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Cin Resistance Zasw(on) Zasw(off) RB1 RB2 MR audio switch ON state impedance audio switch OFF state impedance bias resistance 1 bias resistance 2 resistance matching 50 2 7 14 10 20 150 13 26 1 M k k % Parameter input capacitance Conditions pin to AGND Min Typ Max 10 Unit pF Capacitance
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14. Dynamic characteristics
Table 62. Dynamic characteristics: reset and clock VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol Reset tW(RESET_N) fclk fclk_I2C fclk(dda) external RESET_N pulse width clock frequency I2C-bus clock frequency TX_PULSE_EN = 1 data-during-audio clock frequency bit PWR_DN = 0
[1]
Parameter
Conditions
Min 10 70 3.5 35 5.6 7 5.6
Typ 110 5.0 8 10 8
Max 150 7.0 80 10.4 13 10.4
Unit s kHz MHz MHz ms s ms
Internal clock
td(PD-CLKstop) delay time from power-down to clock stop tstartup(lclk) td(clkstp)
[1]
LazyClock start-up time clock stop delay time
LazyClock for interrupts, registers, and power-down and wake-up timer.
Table 63. Dynamic characteristics: VBUS comparator timing VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol td(VA_VBUS_VLD) Parameter VA_VBUS_VLD delay time Conditions Min 20 Typ Max 300 Unit s
Table 64. Dynamic characteristics: bus turnaround timing (USB bidirectional mode) VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; CL = 50 pF; RPU = 1.5 k on DP to VTERM; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol tTOI tTIO Parameter bus turnaround time (O/I) bus turnaround time (I/O) Conditions OE_N/INT_N to DAT/VP and SE0/VM; see Figure 18 OE_N/INT_N to DAT/VP and SE0/VM; see Figure 18 Min 0 0 Typ Max 5 5 Unit ns ns
Table 65. Dynamic characteristics: analog I/O pins DP and DM VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; CL = 50 pF; RPU = 1.5 k on DP to VTERM; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol tLR Parameter transition time: rise time Conditions CL = 200 pF to 600 pF; 1.5 k pull-up on pin DM enabled; 10 % to 90 % of |VOH - VOL|; see Figure 14 CL = 200 pF to 600 pF; 1.5 k pull-up on pin DM enabled; 90 % to 10 % of |VOH - VOL|; see Figure 14 Min 75 Typ Max 300 Unit ns Driver characteristics (low-speed)
tLF
transition time: fall time
75
-
300
ns
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Table 65. Dynamic characteristics: analog I/O pins DP and DM ...continued VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; CL = 50 pF; RPU = 1.5 k on DP to VTERM; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol FRFM VCRS Parameter differential rise time/fall time matching output signal crossover voltage rise time fall time differential rise time/fall time matching output signal crossover voltage driver propagation delay (LOW to HIGH) driver propagation delay (HIGH to LOW) HIGH to OFF-state propagation delay LOW to OFF-state propagation delay OFF-state to HIGH propagation delay OFF-state to LOW propagation delay Conditions excluding the first transition from idle state excluding the first transition from idle state; see Figure 15 CL = 50 pF; 10 % to 90 % of |VOH - VOL|; see Figure 14 CL = 50 pF; 90 % to 10 % of |VOH - VOL|; see Figure 14 excluding the first transition from idle state excluding the first transition from idle state; see Figure 15 DAT/VP, SE0/VM to DP, DM; see Figure 15 and Figure 19 DAT/VP, SE0/VM to DP, DM; see Figure 15 and Figure 19 OE_N/INT_N to DP, DM; see Figure 16 and Figure 20 OE_N/INT_N to DP, DM; see Figure 16 and Figure 20 OE_N/INT_N to DP, DM; see Figure 16 and Figure 20 OE_N/INT_N to DP, DM; see Figure 16 and Figure 20
[1] [1]
Min 80 1.3
Typ -
Max 125 2.0
Unit % V
Driver characteristics (full-speed) tFR tFF FRFM VCRS 4 4 90 1.3 20 20 111.1 2.0 ns ns % V
Driver timing tPLH(drv) tPHL(drv) tPHZ tPLZ tPZH tPZL 18 18 15 15 15 15 ns ns ns ns ns ns
Receiver timing Differential receiver tPLH(rcv) tPHL(rcv) receiver propagation delay (LOW to HIGH) receiver propagation delay (HIGH to LOW) DP, DM to RCV; see Figure 17 and Figure 21 DP, DM to RCV; see Figure 17 and Figure 21 15 15 ns ns
Single-ended receiver tPLH(se) tPHL(se) single-ended propagation DP, DM to DAT/VP, SE0/VM; delay (LOW to HIGH) see Figure 17 and Figure 21 single-ended propagation DP, DM to DAT/VP, SE0/VM; delay (HIGH to LOW) see Figure 17 and Figure 21 18 18 ns ns
[1]
tFR/tFF.
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Table 66. Dynamic characteristics: analog I/O pin ID VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; CL = 50 pF; RPU = 1.5 k on DP to VTERM; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol tPH_ID_INT tPH_ID_WT Parameter ID interrupt pulse width ID interrupt wait time Conditions Min 4 4 Typ Max 8 8 Unit ms ms
Table 67. Dynamic characteristics: audio switches VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; CL = 50 pF; RPU = 1.5 k on DP to VTERM; Tamb = -40 C to +85 C; unless otherwise specified. Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 C; unless otherwise specified. Symbol PSRR Parameter power supply rejection ratio Conditions noise on VCC = 0.5 V (p-p) at f = 217 Hz over audio range of 20 Hz to 20 kHz; see Section 14.1 audio voltage = 1 V, f = 1 kHz; see Section 14.2 audio voltage = 2.3 V, f = 1 kHz; see Section 14.1 audio voltage = 2.0 V, f = 1 kHz; see Section 14.1 iso(d-a) data to audio isolation USB 12 Mbit/s active on DP and DM, < 20 kHz signal components observed on the SPKR_L and SPKR_R/MIC pins; see Section 14.3 Min Typ Max -80 Unit dB
ct(audio) THD
crosstalk audio total harmonic distortion
-
-
-66 1 0.3 -70
dB % % dB
Vio(aud)
audio input or output voltage range
0.1
-
2.3
V
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1.8 V logic input 0.9 V tFR, tLR VOH 90 % 90 % tFF, tLF 0V tPLH(drv) VOH 10 %
004aaa572
0.9 V
tPHL(drv)
VOL
10 %
differential data lines VOL
VCRS
VCRS
004aaa573
Fig 14. Rise time and fall time
Fig 15. Timing of DAT/VP and SE0/VM to DP and DM
2.0 V 0.9 V differential data lines 0.8 V VCRS tPLH(rcv) tPLH(se) VOH logic output
004aaa574
1.8 V logic 0.9 V input 0V VOH differential data lines VOL tPZH tPZL VCRS VOL + 0.3 V
VCRS tPHL(rcv) tPHL(se)
tPHZ tPLZ VOH - 0.3 V
0.9 V
0.9 V
004aaa575
VOL
Fig 16. Timing of OE_N/INT_N to DP and DM
Fig 17. Timing of DP and DM to RCV, DAT/VP and SE0/VM
OE_N/INT_N
tTOI
tTIO
DAT/VP SE0/VM
output
input
output
004aaa545
Fig 18. SIE interface bus turnaround timing
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USB OTG transceiver with carkit support
VTERM VREG D.U.T. DP or DM
1.5 k 33
test point
CL
15 k
004aaa725
Load capacitance CL = 50 pF (minimum or maximum timing).
Fig 19. Load on pins DP and DM
33
test point
500
D.U.T.
DP or DM
50 pF
V
004aaa517
V = 0 V for tPZH and tPHZ. V = VREG for tPZL and tPLZ.
Fig 20. Load on pins DP and DM for enable time and disable time
test point D.U.T.
10 pF
004aaa669
Fig 21. Load on pins SE0/VM, DAT/VP and RCV
14.1 Test configurations
Table 68. Parameter Termination impedances Test configurations Pins or switches DP DM SPKR_R SPKR_L MIC Switch positions S1 S2 S3 Measured ports Configuration 1 60 k 60 k 200 200 10 k on off on DP DM Configuration 2 200 , 1.4 V DC 60 k 200 , 1.4 V DC 200 , 1.4 V DC 10 k off on on MIC DM
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4.6 ms 577 s Vmax = 3.4 V to 4.2 V 500 mV Vmin = 2.9 V to 3.7 V 30 s
004aaa519
Fig 22. VCC with 217 Hz noise
14.2 Audio crosstalk test conditions
VCC sweeps from 2.9 V to 4.2 V (DC waveform).
14.2.1 Test 1
* SW2 = on and SW3 = on. * DP is terminated using a 200 resistor, and DM is terminated using a 60 k resistor. * MIC is terminated using a 10 k resistor, and SPKR_L is terminated using a 200
resistor, 1.4 V DC.
* Drive f = 1 kHz, V = 1 V (p-p) to DP; signal on DM must be 66 dB below.
14.2.2 Test 2
* * * *
SW1 = on and SW3 = on. DP and DM are terminated using a 60 k resistor. SPKR_L and SPKR_R are terminated using a 200 resistor, 1.4 V DC. Drive f = 1 kHz, V = 1 V (p-p) to SPKR_R; signal on DM must be 66 dB below.
14.2.3 Test 3
* * * *
SW1 = on and SW3 = on. DP and DM terminated using a 60 k resistor. SPKR_L and SPKR_R terminated using a 200 resistor, 1.4 V DC. Drive f = 1 kHz, V = 1 V (p-p) to SPKR_L; signal on DP must be 66 dB below.
14.3 Data to audio isolation test conditions * * * * * *
VCC is swept from 2.9 V to 4.2 V (DC waveform). 12 Mbit/s USB data is to be active on the DP and DM pins. All audio switches must be left open. MIC must be terminated using a 10 k resistor. SPKR_L and SPKR_R are each to be terminated using a 200 resistor. Taking an FFT on the SPKR_R/MIC and SPKR_L pins, USB data components below 20 kHz will be < -70 dB below the USB data level (3.6 V).
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USB OTG transceiver with carkit support
14.4 I2C-bus characteristics
SDA tf
tf
tLOW
tr
tSU;DAT
tHD;STA
tSP
tr
tBUF
SCL tHD;STA S tSU;STA Sr tSU;STO
tHD;DAT
tHIGH
P
S
004aaa216
Fig 23. Definition of timing for standard mode or fast mode devices on the I2C-bus Table 69. Characteristics of I/O stages of I2C-bus lines (SDA, SCL) Conditions Standard mode Min fSCL tHD;STA tLOW tHIGH tSU;STA tSU;DAT tHD;DAT tr tf tSU;STO tBUF tSP SCL clock frequency hold time (repeated) START condition LOW period of the SCL clock HIGH period of the SCL clock set-up time for a repeated START condition data set-up time data hold time rise time of both SDA and SCL signals fall time of both SDA and SCL signals set-up time for STOP condition bus free time between a STOP and START condition pulse width of spikes that must be suppressed by the input filter 0 4.0 4.7 4.0 4.7 250 0 4.0 4.7 not applicable Max 100 1000 300 not applicable 20 + Fast mode Min 0 0.6 1.3 0.6 0.6 100 0 0.1Cb[1] Max 400 0.9 300 300 50 kHz s s s s ns s ns ns s s ns Unit
Symbol Parameter
20 + 0.1Cb[1] 0.6 1.3 0
[1]
Cb is the capacitance load for each bus line in pF. If mixed with high-speed mode devices, faster fall times are allowed.
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xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
Product data sheet Rev. 01 -- 24 May 2007
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15. Application information
NXP Semiconductors
VCC(I/O)
R1 10 k SW1 SW-PB C10 0.1 F C2 0.1 F
VCC(I/O)
VCC
VCC(I/O)
C1 1 F
VCC(I/O) OTG CONTROLLER SDA SCL INT_N
R8 100 k R2 3.3 k R3 3.3 k R4 10 k R5 10 k
ADR/PSW SDA SCL RESET_N INT_N CR_INT VREG SERVICE_N
1 2 3 4 5
24 23 22 21 20
VCC(I/O) CPGND C_B C_A VCC VBUS ID AGND DP DM DAT/VP SE0/VM
C6 0.1 F C9 4.7 F (LOW ESR) R6 33 R7 33 C4 220 nF
SHIELD SHIELD SHIELD SHIELD GND ID D+ D- VBUS
9 8 7 6 USB MINI-AB 5 RECEPTACLE 4 3 2
6 ISP1302HN 19 7 8 9 10 11 12 DGND 18 17 16 15 14 13
OE_N OE_N/INT_N SE0 DAT SPKR_L SPKR_R/MIC RCV CODEC SPKR_L SPKR_R MIC
C11 0.47 F C12 0.47 F C13 0.47 F C5 0.1 F
USB OTG transceiver with carkit support
1
004aaa816
ISP1302
51 of 63
The figure shows the HVQFN pinout. For the WLCSP ballout, see Table 2.
Fig 24. Application diagram
NXP Semiconductors
ISP1302
USB OTG transceiver with carkit support
16. Package outline
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm
SOT616-3
D
B
A
terminal 1 index area A A1 E c
detail X
e1
1/2 e
C b 12 vMCAB wMC 13 y1 C y
e 7 L 6
e
Eh
1/2 e
e2
1 18 terminal 1 index area
24 Dh 0
19 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.1 3.9 Dh 2.75 2.45 E (1) 4.1 3.9 Eh 2.75 2.45 e 0.5 e1 2.5 e2 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT616-3 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 04-11-19 05-03-10
Fig 25. Package outline SOT616-3 (HVQFN24)
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USB OTG transceiver with carkit support
WLCSP25: wafer level chip-size package; 25 bumps; 2.5 x 2.5 x 0.6 mm
ISP1302UK
D
B
A
bump A1 index area A2 E A A1
detail X
e1 e b v w
M M
CAB C
C y
E D
e
C B A 1 2 3 4 5
e2
X
0 DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.64 A1 0.26 0.22 A2 0.38 0.34 b 0.34 0.30 D 2.5 2.4 E 2.5 2.4 e 0.5 e1 2
1 scale
2
3 mm
e2 2
v 0.01
w 0.04
y 0.02
OUTLINE VERSION ISP1302UK
REFERENCES IEC JEDEC JEITA
EUROPEAN PROJECTION
ISSUE DATE 05-09-28 05-09-30
Fig 26. Package outline ISP1302UK (WLCSP25)
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17. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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17.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 27) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 70 and 71
Table 70. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 71. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 27.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 27. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
18. Additional soldering information
A more in-depth account of soldering WLCSP (Wafer-Level Chip-Size Package) can be found in Application Note AN10439 "Wafer Level Chip Scale Package".
19. Abbreviations
Table 72. Acronym ATX FFT HNP I2C-bus LSB MIC NRZ OTG POR PORP RxD SE0 SIE SoC SOF
ISP1302_1
Abbreviations Description Analog USB Transceiver Fast Fourier Transform Host Negotiation Protocol Inter IC-bus Least Significant Bit Microphone Non-Return-to-Zero On-The-Go Power-On Reset Power-On Reset Pulse Receive Data Single-Ended Zero Serial Interface Engine System-on-a-Chip Start-Of-Frame
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Abbreviations ...continued Description Session Request Protocol Transmit Data Universal Asynchronous Receiver-Transmitter Universal Serial Bus Wafer-Level Chip-Scale Package
Table 72. Acronym SRP TxD UART USB WLCSP
20. References
[1] [2] [3] [4] [5] [6] [7] [8] [9] Universal Serial Bus Specification Rev. 2.0 On-The-Go Supplement to the USB Specification Rev. 1.2 On-The-Go Transceiver Specification (CEA-2011) USB Carkit Specification (CEA-936-A), November 2005 ECN_27%_Resistor (Pull-up/pull-down Resistors ECN) The I2C-bus specification; ver. 2.1 Human Body Model (JESD22-A114D) Machine Model (JESD22-A115-A) Charge Device Model (JESD22-C101-C)
21. Revision history
Table 73. ISP1302_1 Revision history Release date 20070524 Data sheet status Product data sheet Change notice Supersedes Document ID
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22. Legal information
22.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
22.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
22.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to
22.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
23. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
ISP1302_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 24 May 2007
58 of 63
NXP Semiconductors
ISP1302
USB OTG transceiver with carkit support
24. Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 ID pin status for various applications . . . . . . . . .9 ID pull-down control . . . . . . . . . . . . . . . . . . . . .10 Transceiver driver operating setting . . . . . . . . .15 USB functional mode: transmit operation . . . .15 Differential receiver operation settings . . . . . . .15 USB functional mode: receive operation . . . . .15 Possible combinations of I2C-bus address and the PSW polarity . . . . . . . . . . . . . . . . . . . .17 ISP1302 power modes summary . . . . . . . . . . .18 ISP1302 pin states in disable and isolate modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 USB functional modes: I/O values . . . . . . . . . .19 Summary of device operating modes . . . . . . .21 Transparent general-purpose buffer mode . . . .21 Register overview . . . . . . . . . . . . . . . . . . . . . .22 Vendor ID register (address R = 00h to 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .23 Product ID register (address R = 02h to 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .23 Version ID register (address R = 14h to 15h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Version ID register (address R = 14h to 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .23 Mode Control 1 register (address S = 04h, C = 05h) bit allocation . . . . . . . . . . . . . . . . . . .24 Mode Control 1 register (address S = 04h, C = 05h) bit description . . . . . . . . . . . . . . . . . .24 Mode Control 2 register (address S = 12h, C = 13h) bit allocation . . . . . . . . . . . . . . . . . . .24 Mode Control 2 register (address S = 12h, C = 13h) bit description . . . . . . . . . . . . . . . . . .25 Audio Control register (address S = 16h, C = 17h) bit allocation . . . . . . . . . . . . . . . . . . .25 Audio Control register (address S = 16h, C = 17h) bit description . . . . . . . . . . . . . . . . . .25 OTG Control register (address S = 06h, C = 07h) bit allocation . . . . . . . . . . . . . . . . . . .25 OTG Control register (address S = 06h, C = 07h) bit description . . . . . . . . . . . . . . . . . .26 Misc Control register (address S = 18h, C = 19h) bit allocation . . . . . . . . . . . . . . . . . . .26 Misc Control register (address S = 18h, C = 19h) bit description . . . . . . . . . . . . . . . . . .26 Carkit Control register (address S = 1Ah, C = 1Bh) bit allocation . . . . . . . . . . . . . . . . . . .27 Carkit Control register (address S = 1Ah, C = 1Bh) bit description . . . . . . . . . . . . . . . . . . 27 Table 32. Transmit Positive Width register (address R/W = 1Ch) bit description . . . . . . . . . . . . . . . 28 Table 33. Transmit Negative Width register (address R/W = 1Dh) bit description . . . . . . . . . . . . . . . 28 Table 34. Receive Polarity Recovery register (address R/W = 1Eh) bit description . . . . . . . . . . . . . . . 28 Table 35. Carkit Interrupt Delay register (address R/W = 1Fh) bit description . . . . . . . . . . . . . . . 28 Table 36. OTG Status register (address R = 10h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 37. OTG Status register (address R = 10h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 38. Interrupt Source register (address R = 08h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 39. Interrupt Source register (address R = 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 40. Interrupt Latch register (address S = 0Ah, C = 0Bh) bit allocation . . . . . . . . . . . . . . . . . . . 31 Table 41. Interrupt Latch register (address S = 0Ah, C = 0Bh) bit description . . . . . . . . . . . . . . . . . . 31 Table 42. Interrupt Enable Low register (address S = 0Ch, C = 0Dh) bit allocation . . . . . . . . . . . 31 Table 43. Interrupt Enable Low register (address S = 0Ch, C = 0Dh) bit description . . . . . . . . . . 32 Table 44. Interrupt Enable High register (address S = 0Eh, C = 0Fh) bit allocation . . . . . . . . . . . 32 Table 45. Interrupt Enable High register (address S = 0Eh, C = 0Fh) bit description . . . . . . . . . . 32 Table 46. I2C-bus byte transfer format . . . . . . . . . . . . . . 33 Table 47. I2C-bus slave address bit allocation . . . . . . . . 33 Table 48. I2C-bus slave address bit description . . . . . . . 34 Table 49. Transfer format description for a one-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 50. Transfer format description for a multiple-byte write . . . . . . . . . . . . . . . . . . . . . . 34 Table 51. Transfer format description for current address read . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 52. Transfer format description for a single-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 53. Transfer format description for a multiple-byte read . . . . . . . . . . . . . . . . . . . . . . 36 Table 54. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 55. Recommended operating conditions . . . . . . . . 39 Table 56. Static characteristics: supply pins . . . . . . . . . . 40 Table 57. Static characteristics: digital pins . . . . . . . . . . 41 Table 58. Static characteristics: analog I/O pins DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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ISP1302_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 24 May 2007
59 of 63
NXP Semiconductors
ISP1302
USB OTG transceiver with carkit support
Table 59. Static characteristics: analog I/O pin ID . . . . . .42 Table 60. Static characteristics: charge pump . . . . . . . . .42 Table 61. Static characteristics: analog I/O pins SPKR_R/MIC and SPKR_L . . . . . . . . . . . . . . .43 Table 62. Dynamic characteristics: reset and clock . . . . .44 Table 63. Dynamic characteristics: VBUS comparator timing . . . . . . . . . . . . . . . . . . . . . .44 Table 64. Dynamic characteristics: bus turnaround timing (USB bidirectional mode) . . . . . . . . . . .44 Table 65. Dynamic characteristics: analog I/O pins DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Table 66. Dynamic characteristics: analog I/O pin ID . . .46 Table 67. Dynamic characteristics: audio switches . . . . .46 Table 68. Test configurations . . . . . . . . . . . . . . . . . . . . . .48 Table 69. Characteristics of I/O stages of I2C-bus lines (SDA, SCL) . . . . . . . . . . . . . . . . . . . . . . .50 Table 70. SnPb eutectic process (from J-STD-020C) . . .55 Table 71. Lead-free process (from J-STD-020C) . . . . . .55 Table 72. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .56 Table 73. Revision history . . . . . . . . . . . . . . . . . . . . . . . .57
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ISP1302_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 24 May 2007
60 of 63
NXP Semiconductors
ISP1302
USB OTG transceiver with carkit support
25. Figures
Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin configuration HVQFN24 (top view) . . . . . . . . .4 Pin configuration HVQFN24 (bottom view) . . . . . .4 Pin configuration WLCSP25 (top view) . . . . . . . . .5 Pin configuration WLCSP25 (bottom view) . . . . . .5 DP and DM pull-up and pull-down resistors. . . . .11 Audio bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Audio data control . . . . . . . . . . . . . . . . . . . . . . . .13 Internal power-on reset timing . . . . . . . . . . . . . . .16 Using an external charge pump . . . . . . . . . . . . . .17 Writing data to the ISP1302 registers . . . . . . . . .35 Current address read . . . . . . . . . . . . . . . . . . . . . .36 Random address read . . . . . . . . . . . . . . . . . . . . .37 Rise time and fall time . . . . . . . . . . . . . . . . . . . . .47 Timing of DAT/VP and SE0/VM to DP and DM . .47 Timing of OE_N/INT_N to DP and DM . . . . . . . .47 Timing of DP and DM to RCV, DAT/VP and SE0/VM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 SIE interface bus turnaround timing. . . . . . . . . . .47 Load on pins DP and DM. . . . . . . . . . . . . . . . . . .48 Load on pins DP and DM for enable time and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Load on pins SE0/VM, DAT/VP and RCV . . . . . .48 VCC with 217 Hz noise . . . . . . . . . . . . . . . . . . . . .49 Definition of timing for standard mode or fast mode devices on the I2C-bus. . . . . . . . . . . . . . . .50 Application diagram . . . . . . . . . . . . . . . . . . . . . . .51 Package outline SOT616-3 (HVQFN24) . . . . . . .52 Package outline ISP1302UK (WLCSP25) . . . . . .53 Temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
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ISP1302_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 24 May 2007
61 of 63
NXP Semiconductors
ISP1302
USB OTG transceiver with carkit support
26. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.4 7.5 7.6 7.7 7.8 7.9 7.9.1 7.9.2 7.9.3 7.9.4 7.10 7.11 7.11.1 7.11.2 7.12 7.13 8 8.1 8.1.1 8.1.2 8.1.3 8.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 9 9.1 9.1.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 8 Serial controller. . . . . . . . . . . . . . . . . . . . . . . . . 8 VBUS charge pump . . . . . . . . . . . . . . . . . . . . . . 8 VBUS comparators. . . . . . . . . . . . . . . . . . . . . . . 8 VBUS valid comparator . . . . . . . . . . . . . . . . . . . 8 Session valid comparator . . . . . . . . . . . . . . . . . 8 Session end comparator. . . . . . . . . . . . . . . . . . 8 ID detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pull-up and pull-down resistors. . . . . . . . . . . . 10 3.3 V DC-DC regulator . . . . . . . . . . . . . . . . . . 11 Carkit DP interrupt detector . . . . . . . . . . . . . . 11 Audio bypass . . . . . . . . . . . . . . . . . . . . . . . . . 12 Audio data control. . . . . . . . . . . . . . . . . . . . . . 12 Audio timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TxD pulse generator . . . . . . . . . . . . . . . . . . . . 13 Stereo interrupt detector . . . . . . . . . . . . . . . . . 14 RxD pulse converter . . . . . . . . . . . . . . . . . . . . 14 Autoconnect . . . . . . . . . . . . . . . . . . . . . . . . . . 14 USB transceiver . . . . . . . . . . . . . . . . . . . . . . . 14 Differential driver. . . . . . . . . . . . . . . . . . . . . . . 14 Differential receiver . . . . . . . . . . . . . . . . . . . . . 15 Power-On Reset (POR) . . . . . . . . . . . . . . . . . 16 I2C-bus device address and external charge pump control . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Modes of operation . . . . . . . . . . . . . . . . . . . . . 18 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 18 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disable mode . . . . . . . . . . . . . . . . . . . . . . . . . 18 Isolate mode . . . . . . . . . . . . . . . . . . . . . . . . . . 18 USB modes. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Transparent modes . . . . . . . . . . . . . . . . . . . . . 20 Transparent UART mode . . . . . . . . . . . . . . . . 20 Transparent audio mode . . . . . . . . . . . . . . . . . 20 Transparent general-purpose buffer mode . . . 20 Data-during-audio mode . . . . . . . . . . . . . . . . . 20 Serial controller . . . . . . . . . . . . . . . . . . . . . . . . 22 Register map . . . . . . . . . . . . . . . . . . . . . . . . . 22 Device identification registers . . . . . . . . . . . . . 22 9.1.1.1 Vendor ID register . . . . . . . . . . . . . . . . . . . . . 9.1.1.2 Product ID register . . . . . . . . . . . . . . . . . . . . . 9.1.1.3 Version ID register . . . . . . . . . . . . . . . . . . . . . 9.1.2 Control registers. . . . . . . . . . . . . . . . . . . . . . . 9.1.2.1 Mode Control 1 register . . . . . . . . . . . . . . . . . 9.1.2.2 Mode Control 2 register . . . . . . . . . . . . . . . . . 9.1.2.3 Audio Control register. . . . . . . . . . . . . . . . . . . 9.1.2.4 OTG Control register . . . . . . . . . . . . . . . . . . . 9.1.2.5 Misc Control register . . . . . . . . . . . . . . . . . . . 9.1.2.6 Carkit Control register . . . . . . . . . . . . . . . . . . 9.1.2.7 Transmit Positive Width register . . . . . . . . . . . 9.1.2.8 Transmit Negative Width register . . . . . . . . . . 9.1.2.9 Receive Polarity Recovery register . . . . . . . . 9.1.2.10 Carkit Interrupt Delay register . . . . . . . . . . . . 9.1.2.11 OTG Status register . . . . . . . . . . . . . . . . . . . . 9.1.3 Interrupt registers . . . . . . . . . . . . . . . . . . . . . . 9.1.3.1 Interrupt Source register . . . . . . . . . . . . . . . . 9.1.3.2 Interrupt Latch register . . . . . . . . . . . . . . . . . . 9.1.3.3 Interrupt Enable Low register . . . . . . . . . . . . . 9.1.3.4 Interrupt Enable High register . . . . . . . . . . . . 9.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 9.3.1 I2C-bus byte transfer format . . . . . . . . . . . . . . 9.3.2 I2C-bus device address . . . . . . . . . . . . . . . . . 9.3.3 Write format . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.3.1 One-byte write . . . . . . . . . . . . . . . . . . . . . . . . 9.3.3.2 Multiple-byte write . . . . . . . . . . . . . . . . . . . . . 9.3.4 Read format . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.4.1 Current address read . . . . . . . . . . . . . . . . . . . 9.3.4.2 Random address read: single read . . . . . . . . 9.3.4.3 Random address read: multiple read . . . . . . . 10 Clock wake-up scheme . . . . . . . . . . . . . . . . . . 10.1 Power-down event . . . . . . . . . . . . . . . . . . . . . 10.2 Clock wake-up event . . . . . . . . . . . . . . . . . . . 11 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 12 Recommended operating conditions . . . . . . 13 Static characteristics . . . . . . . . . . . . . . . . . . . 14 Dynamic characteristics . . . . . . . . . . . . . . . . . 14.1 Test configurations . . . . . . . . . . . . . . . . . . . . . 14.2 Audio crosstalk test conditions . . . . . . . . . . . . 14.2.1 Test 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.2 Test 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2.3 Test 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Data to audio isolation test conditions . . . . . . 14.4 I2C-bus characteristics . . . . . . . . . . . . . . . . . . 15 Application information . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22 23 23 23 23 24 25 25 26 27 28 28 28 28 28 29 29 31 31 32 33 33 33 33 34 34 34 35 35 36 36 37 37 38 39 39 40 44 48 49 49 49 49 49 50 51 52
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ISP1302_1
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 -- 24 May 2007
62 of 63
NXP Semiconductors
ISP1302
USB OTG transceiver with carkit support
54 54 54 54 55 56 56 57 57 58 58 58 58 58 58 59 61 62
17 17.1 17.2 17.3 17.4 18 19 20 21 22 22.1 22.2 22.3 22.4 23 24 25 26
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering . . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . Additional soldering information . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 24 May 2007 Document identifier: ISP1302_1

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